Datasheet

Layout
3-2
3.1 Layout
The top-side layer for the TPS54310 EVM is shown in Figure 3–1. The input
capacitors (C8 and C9), bias decoupling capacitor (C3), and bootstrap
capacitor (C7), are all located as close to the IC as possible. In addition, the
feedback compensation components are also kept close to the IC. The
compensation circuit ties to the output voltage at the point of regulation (TP7).
The TPS54310 EVM PWB consists of two layers of 1.5 oz. copper. The bottom
half of the top layer is used as a power ground plane, while the bottom layer
is used as a quiet (analog) ground plane. The two ground planes tie together
at U1 to reduce the noise injected between the two IC ground connections. A
total of 10 vias are used to tie the thermal land area under the TPS54310
device to the thermal plane on the backside of the board.
Figure 3–1. Top Side Assembly