Datasheet
SW1
VIN1
VBST 1
EN1
VFB2
VFB1
GND
VREG5
PGND1
6
VIN2
VBST2
EN2
SW 2
SS
1
5
1
3
SS 2
9
10
11
PGND 2
2
4
7
13
12
14
8
15
16
TPS542951
HTSSOP16
(PowerPAD)
PowerPAD
VFB1
VFB2
VIN1
SW2
VBST2
VBST1
EN1
14
75
6
2
3
4
1
PGND2
PGND1
SW1
VIN2
13
12
11
9
8
SS1
10
GND
SS2
EN2
16 15
VREG5
TPS542951
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SLVSBI4B –JULY 2012–REVISED OCTOBER 2013
DEVICE INFORMATION
HTSSOP PACKAGE
(TOP VIEW)
PIN FUNCTIONS
(1)
PIN
NUMBER I/O DESCRIPTION
NAME
PWP RSA
VIN1 1 3
Power inputs and connects to both high side NFET drains.
I
Supply Input for 5.5V linear regulator.
VIN2 16 2
VBST1 2 4 Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor
I between VBSTx and SWx pins. An internal diode is connected between VREG5 and
VBST2 15 1
VBSTx
SW1 3 5
Switch node connections for both the high-side NFETs and low–side NFETs. Input of
I/O
current comparator.
SW2 14 16
PGND1 4 6
I/O Ground returns for low-side MOSFETs. Input of current comparator.
PGND2 13 15
EN1 5 7
I Enable. Pull High to enable according converter.
EN2 12 14
PG1 6 —
Open drain power good outputs. Low indicates the corresponding output voltage is out of
O
regulation.
PG2 11 —
SS1 — 8
Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program Soft-
O
Start time.
SS2 — 13
VFB1 7 9
I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2 10 12
GND 8 10 I/O Signal GND. Connect sensitive VFBx returns to GND at a single point.
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
VREG5 9 11 O
least 1.0 µF. VREG5 is active when VIN1 is high.
Back Back Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must
PowerPAD™ I/O
side side be connected to GND.
(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
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