Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 16

V = 1.5 V (50 mV/div)

Iout (1 A/div)

t - Time - 100 s/divm

Input Voltage

PGND

SW1

VIN1

VBST1

EN1

VFB2

VFB1

GND

VREG5

PGND1

VIN2

VBST2

EN2

SW2

PG1

PG2

PGND2

TPS54294

HTSSOP16

PGND

SGND

C11

VO1

C21

R11

R21

L11

C31

C32

L12

C12

VO2

C22

R12

R22

(PowerPAD)

TPS54294

www.ti.com

SLVSB00D –OCTOBER 2011–REVISED SEPTEMBER 2013

2A Dual Channel Synchronous Step-Down Switcher with Integrated FET

Check for Samples: TPS54294

FEATURES

APPLICATIONS

• D-CAP2™ Control Mode

• Point-of-Load Regulation in Low Power

Systems for Wide Range of Applications

– Fast Transient Response

– Digital TV Power Supply

– No External Parts Required For Loop

Compensation – Networking Home Terminal

– Compatible with Ceramic Output – Digital Set Top Box (STB)

Capacitors

– DVD Player/Recorder

• Wide Input Voltage Range : 4.5 V to 18 V

– Gaming Consoles and Other

• Output Voltage Range : 0.76V to 7.0V

DESCRIPTION

• Highly Efficient Integrated FETs Optimized for

The TPS54294 is a dual, adaptive on-time D-CAP2™

Low Duty Cycle Applications

mode synchronous buck converter. The TPS54294

– 150 mΩ (High Side) and 100 mΩ (Low Side)

enables system designers to complete the suite of

• High Initial Reference Accuracy

various end equipment’s power bus regulators with a

cost effective, low component count, and low standby

• Low-Side r

DS(on)

Loss-Less Current Sensing

current solution. The main control loops of the

• Fixed Soft Start : 1.0ms

TPS54294 use the D-CAP2™ mode control which

• Non-Sinking Pre-Biased Soft Start

provides a very fast transient response with no

• Powergood

external compensation components. The adaptive on-

time control supports seamless transition between

• 700 kHz Switching Frequency

PWM mode at higher load conditions and Eco-

• Cycle-by-Cycle Over-Current Limit Control

mode™ operation at light loads. Eco-mode™ allows

• OCL/OVP/UVP/UVLO/TSD Protections

the TPS54294 to maintain high efficiency during

lighter load conditions. The TPS54294 is able to

• Adaptive Gate Drivers with Integrated Boost

adapt to both low equivalent series resistance (ESR)

PMOS Switch

output capacitors such as POSCAP or SP-CAP, and

• OCP Constant Due To Thermally Compensated

ultra-low ESR, ceramic capacitors. The device

DS(on)

with 4000ppm/℃℃

provides convenient and efficient operation with input

• 16-Pin HTSSOP, 16-Pin VQFN

voltages from 4.5V to 18V.

• Auto-Skip Eco-mode™　　for High Efficiency at

The TPS54294 is available in a 4.4mm × 5.0mm 16-

Light Load

pin TSSOP (PWP) package, and 4mm x 4mm 16-pin

VQFN (RSA) package specified for an ambient

temperature range from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2, Eco-mode, Eco-Mode, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 2A Dual Channel Synchronous Step-Down Switcher with Integrated FET Check for Samples: TPS54294 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • • • D-CAP2™ Control Mode – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors Wide Input Voltage Range : 4.5 V to 18 V Output Voltage Range : 0.76V to 7.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VALUES Supply input voltage range Input voltage range VIN1, VIN2 MAX 4.5 18 VBST1, VBST2 –0.1 24 VBST1, VBST2 (10ns transient) –0.1 27 VBST1–SW1, VBST2–SW2 –0.1 5.7 VFB1, VFB2 –0.1 5.7 EN1, EN2 –0.1 18 SW1, SW2 –1.0 18 SW1, SW2 (10ns transient) Output voltage range MIN –3 21 VREG5, PG1 , PG2 –0.1 5.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT 110 Ω POWER GOOD VPGTH PGx threshold RPG PGx pull-down resistance TPGDLY PGx delay time TPGCOMPSS PGx comparator start-up delay PG from lower VOx (going high) 84% PG from higher VOx (going low) 116% VPGx = 0.5 V 50 Delay for PGx going high 75 1.
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TPS54294 www.ti.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM - 16% VIN1 PG Comp VIN1 +16% PG1 - 32 VBST1 UV1 0.1uF OV1 VO1 SW1 +20 Ref1 Err Com p VFB1 SS1 PGND1 Ref_OCL PGND1 SW1 OCP1 EN1 EN2 EN Logic PGND1 SW1 ZC1 EN Logic VIN1 GND VREG5 CH1 Min- off timer 5VREG 1.0uF . CH2 Min- off timer SS1 Fixed SoftStart UV1 UV2 OV1 OV2 UVLO TSD SS2 - 32 Ref1 Ref2 REF UVLO Protection Logic VIN2 VIN2 VBST2 UV2 0.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 OVERVIEW The TPS54294 is a 2A/2A dual synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com POWERGOOD The TPS54294 has power-good outputs that are measured on VFBx. The power-good function is activated after the soft-start has finished. If the output voltage is within 16% of the target voltage, the internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay. During start-up, this internal delay starts after 1.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 200 VIN1 = VIN2 = 12V EN1 = EN2 = ON Ivccsdn - Shutdown Current - mA 180 160 140 120 100 80 60 40 20 0 -50 0 50 100 150 TJ - Junction Temperature - °C Figure 2. Input Shutdown Current vs Junction Temperature 100 3.4 90 3.38 80 3.36 VO - Output Voltage - V EN Input Current - mA Figure 1.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 1.55 1.54 Vo1(50 mV/div) VO - Output Voltage - V 1.53 Io2 = 1 A 1.52 1.51 1.5 IO1(1 A/div) Io2 = 10m A 1.49 1.48 1.47 1.46 1.45 0 2 4 6 8 10 12 VI - Input Voltage - V 14 16 18 20 t - Time - 100 ms/div Figure 7. VO2=1.5V Output Voltage vs Input Voltage Figure 8. VO1=3.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 100 100 VI = 18 V 90 VI = 12 V 90 80 VI = 5 V 70 Efficiency - % Efficiency - % 80 60 50 40 VI = 12 V VI = 18 V VI = 5 V 70 60 30 20 50 10 40 0 0.001 0.01 IO - Output Current - A 0.1 0 Figure 13. VO1=3.3V, Efficiency vs Output Current 1.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 800 VI = 12 V Vo1 = 3.3 V (10 mV/div) fsw - Switching Frequency - kHz 700 600 500 400 SW1 (5 V/div) 300 200 100 0 0.01 0.1 1 IO - Output Current - A 10 t - Time - 400 ns/div Figure 19. VO2=1.5V, SW-frequency vs Output Current Figure 20. VO1=3.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 DESIGN GUIDE Step By Step Design Procedure To • • • begin the design process, you must know a few application parameters: Input voltage range Output voltage Output current In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated switching frequency of 700 kHz is used. VINx 12V ± 10% C11 10 mF VO1 1.05 V L11 1.5 mH C31 0.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS545294. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 Bootstrap Capacitor Selection A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is recommended to use ceramic capacitors with a dielectric of X5R or better. VREG5 Capacitor Selection A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is recommended to use a ceramic capacitor with a dielectric of X5R or better.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.com Layout Considerations 1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal pad. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 VIN2 VIN HIGH FREQUENCY BYPASS CAPACITOR ～0.1µF VIN1 1 16 VIN2 VBST 1 2 15 VBST2 SW 1 3 14 SW2 4 13 PGND 2 EN1 5 12 EN2 PG1 6 11 PG2 VFB1 7 10 VFB2 GND 8 9 PGND 1 Symmetrical Layout for CH1 and CH2 VIN INPUT BYPASS CAPACITOR 10µF x2 Switching noise flows through IC and CIN . It avoids the thermal Pad. OUTPUT FILTER CAPACITOR VO2 OUTPUT INDUCTOR Recommend to keep distance more than 3-4mm.
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TPS54294 SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 www.ti.
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TPS54294 www.ti.com SLVSB00D – OCTOBER 2011 – REVISED SEPTEMBER 2013 REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (October 2011) to Revision A Page • Added input voltage range for VFB1, VFB2 to Absolute Maximum Ratings ........................................................................ 2 • Added input voltage range for VFB1, VFB2 to Recommended Operating Conditions .........................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS54294PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS54294PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 TPS54294RSAR QFN RSA 16 3000 330.0 12.4 4.25 TPS54294RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.6 1.6 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54294PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54294PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54294RSAR QFN RSA 16 3000 367.0 367.0 35.0 TPS54294RSAT QFN RSA 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.