Datasheet

11GND
UDG-09124
5EN1
6EN2
10 mA
(max)
10 mA
(max)
Internal
Control
Output
Undervoltage
Detect
FB1
FB2
TSD
SD1
SD2
UVLO
2.4 MHz
Oscilator
Divide by
2/4/8
Ramp
Gen 1
Ramp
Gen 2
CLK1
CLK2
f(I
SLOPE1
)
f(I
SLOPE2
)
7FB1
+
Soft Start
1
0.8 V
REF
SD1
8COMP1
10FB2
+
Soft Start
2
0.8 V
REF
SD2
9COMP2
f(I
DRAIN1
) + DC(ofst)
+
S Q
QR
R
+
Current
Comparator
BP 2
1
3
Anti-Cross
Conduction
BP
CLK1
BOOT1
PVDD1
SW1
f(I
DRAIN1
)
f(I
MAX1
)
Overcurrent Comp
f(I
SLOPE1
)
I
DRAIN1
FET
Switch
CLK1
4 PGND1
f(I
DRAIN2
) + DC(ofst)
+
S Q
QR
R
+
Current
Comparator
BP 15
16
14
Anti-Cross
Conduction
BP
CLK2
BOOT2
PVDD2
SW2
f(I
DRAIN2
)
f(I
MAX2
)
Overcurrent Comp
f(I
SLOPE2
)
I
DRAIN2
FET
Switch
CLK2
13 PGND2
12BP
5.25-V
Regulator
References
PVDD2
FET
Switch
TPS54290, TPS54291, TPS54292
www.ti.com SLUS973 –OCTOBER 2009
BLOCK DIAGRAM
Figure 11. Block Diagram
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