Datasheet

( ) ( )
OUT OUT
MAX1 MAX2
IN m in IN m in
V V
3.3 1.2
D 0.413 D 0.15
V 8.0 V 8.0
» = = ¾¾® » = =
( ) ( )
OUT OUT
MIN1 MIN2
IN max IN max
V V
3.3 1.2
D 0.236 D 0.086
V 14 V 14
» = = ¾¾® » = =
( ) ( )
Lrip1 max OUT max
I 0.30 I 0.3 1.5 A 0.450 A= ´ = ´ =
( ) ( )
Lrip2 max OUT max
I 0.30 I 0.3 2.5 A 0.750 A= ´ = ´ =
( )
( )
f
OUT
IN max
MIN1 MIN
SW
LRIP max
V V
1 14 3.3 1
L D 0.236 9.35 H
I 0.45 A 600kHz
-
-
» ´ ´ = ´ ´ = m
( )
( )
f
OUT
IN max
MIN2 MIN
SW
LRIP max
V V
1 14 1.2 1
L D 0.086 2.45 H
I 0.75 A 600 kHz
-
-
» ´ ´ = ´ ´ = m
TPS54290, TPS54291, TPS54292
www.ti.com SLUS973 –OCTOBER 2009
The list of materials for this application is shown below in Table 2. The efficiency, line regulation and load
regulation from printed circuit boards built using this design are shown in Figure 23 and Figure 24.
Figure 21. TPS54291 Design Example 1 Schematic
Step by Step Design Procedure
Duty Cycle Estimation
The duty cycle of the main switching FET is estimated by Equation 16 and Equation 17.
(16)
(17)
Inductor Selection
The peak to peak ripple should be limited to between 20% and 30% of the maximum output current.
(18)
(19)
The minimum inductor size can be estimated by Equation 20 and Equation 21.
(20)
(21)
The standard inductor values of 8.2 µH and 3.3 µH are selected for Channel 1 and Channel 2 respectively. The
actual ripple currents are estimated by Equation 22 and Equation 23.
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