Datasheet

( )
( )
(
)
2
2
O
D(cond) DS(on)LS O
DS on HS
I
P R D R 1 D I
12
æ ö
D
ç ÷
= ´ + ´ - ´ +
ç ÷
è ø
( ) ( )
( )
2
IN OSS OSS S
D(SW )
V C HS C LS f
P
2
´ + ´
=
D D(cond)output1 D(SW )output1 D(cond)output2 D(SW )output2 IN
P P P P P V Iq= + + + + ´
( )
J A D TH(pkg) TH(pad amb)
T T P
-
= + ´ q + q
TPS54290, TPS54291, TPS54292
www.ti.com SLUS973 –OCTOBER 2009
OVER-TEMPERATURE PROTECTION AND JUNCTION TEMPERATURE RISE
The over temperature thermal protection limits the maximum power to be dissipated at a given operating ambient
temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is
limited by the maximum allowable junction operating temperature. The device junction temperature is a function
of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature
should reach the thermal shutdown level, the TPS5429x shuts off both PWMs and remain in this state until the
die temperature drops below 125°C, at which time the device restarts.
The first step in determining the device junction temperature is to calculate the power dissipation. The power
dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by
each MOSFET is composed of conduction losses and switching losses. The total conduction loss in the high side
and low side MOSFETs for each channel is given by Equation 12.
(12)
where
• I
O
is the DC output current,
• ΔI
O
is the peak-to-peak ripple current in the inductor
Notice the impact of operating duty cycle on the result.
The switching loss for each channal is approximated by Equation 13.
(13)
where
• C
OSS(HS)
is the output capacitance of the high-side MOSFET
• C
OSS(LS)
is the output capacitance of the low-side MOSFET
• ƒ
S
is the switching frequency
The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal
regulator.
(14)
The temperature rise of the device junction is dependent on the thermal impedance from junction to the mounting
pad (See Package Dissipation Ratings), plus the thermal impedance from the thermal pad to ambient. The
thermal impedance from the thermal pad to ambient is dependent on the PCB layout (PowerPAD interface to the
PCB, the exposed pad area) and airflow (if any). See PCB Layout Guidelines, Additional References.
The operating junction temperature is shown in Equation 15.
(15)
where
• θth is the thermal impedance
BYPASSING AND FILTERING
As with any integrated circuit, supply bypassing is important for jitter free operation. To improve the noise
immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.
• PVDD1 to GND – Use a 10 µF ceramic capacitor
• PVDD2 to GND – Use a 10 µF ceramic capacitor
• BP to GND – Use a 4.7 µF Ceramic capacitor
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :TPS54290 TPS54291 TPS54292