Datasheet

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Voltage Setting
FB
OUT1 FB
V R2
R4
V V
´
=
-
(32)
FB
OUT2 FB
V R9
R7
V V
´
=
-
(33)
Compensation Capacitors
f
ESR(zero)
1
2 C ESR
=
´ p ´ ´
(34)
f
f
ZERO(desired)
ESR(zero)
R4
R5
1
=
æ ö
æ ö
ç ÷
-
ç ÷
ç ÷
ç ÷
è ø
è ø
(35)
EQ
1
R R5
1 1
R2 R4
= +
æ ö
æ ö æ ö
+
ç ÷
ç ÷ ç ÷
è ø è ø
è ø
(36)
f
EQ ESR(zero)
1
C8
2 R
=
´ p ´ ´
(37)
TPS54283 , , TPS54286
SLUS749C JULY 2007 REVISED OCTOBER 2007
The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 k and 50 k to
maintain a balance between power dissipation and noise sensitivity. For this design, 20 k is selected.
The lower resistors, R4 and R7 are found using the following equations.
R2 = R9 = 20 k
V
FB
= 0.80 V
R4= 3.80 k (3.83 k standard value is used)
R7= 6.40 k (6.34 k standard value is used)
Checking the ESR zero of the output capacitors:
C = 100 µ F
ESR = 400 m
ESR
(zero)
= 3980 Hz
Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4
and R7 to compensate for the electrolytic capacitors' ESR and add a zero about 40 kHz.
f
ESR(zero)
= 4 kHz
f
ESR(desired)
= 40 kHz
R4 = 3.83 k
R5 = 424 (422 selected)
R7 = 6.34 k
R8 = 702 (698 selected)
R2 = R9 = 20 k
REQ1 = 3.63 k
REQ2 = 5.51 k
C8 = 10.9 nF (10 nF selected)
C15 = 7.22 nF (6800 pF selected)
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