Datasheet

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Cascading Supply Operation
1
2
3
4
14
13
12
11
PVDD2
BOOT2
SW2
BP
PVDD1
BOOT1
SW1
GND
TPS54283
5
6
7
10
9
8
SEQ
ILIM2
FB2
EN1
EN2
FB1
OUTPUT1
OUTPUT2
V
IN
UDG-07015
TPS54283 , , TPS54286
SLUS749C – JULY 2007 – REVISED OCTOBER 2007
The preferred sequence of events is:
1. PVDD2 rises above the input UVLO voltage
2. PVDD1 rises with Output 1 disabled until PVDD1 rises above level to support Output 1 regulation.
With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.
DESIGN HINT
An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough
period of time to ensure that PVDD1 can support Output 1 load.
It is possible to source PVDD1 from Output 2 as depicted in Figure 33 and Figure 34 . This configuration may be
preferred if the input voltage is high, relative to the voltage on Output 1.
Figure 33. Schematic Showing Cascading PVDD1 from Output 2
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