Datasheet

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APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

Voltage Reference

Oscillator

Input Undervoltage Lockout (UVLO) and Startup

Enable and Timed Turn On of the Outputs

TPS54283 , , TPS54286

SLUS749C – JULY 2007 – REVISED OCTOBER 2007

The TPS54283 and TPS54286 are dual output non-synchronous converters. Each PWM channel contains an

internally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable,

and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference,

clock oscillator, and output voltage sequencing functions.

DESIGN HINT

The TPS5428x contains internal slope compensation and loop compensation

components; therefore, the external L-C filter must be selected appropriately so that

the resulting control loop meets criteria for stability. This approach differs from an

externally-compensated controller, where the L-C filter is generally selected first, and

the compensation network is found afterwards. (See Feedback Loop and L-C Filter

Selection section.)

NOTE:

Unless otherwise noted, the term TPS5428x applies to both the TPS54283 and

TPS54286. Also, unless otherwise noted, a label with a lowercase x appended implies

the term applies to both outputs of the two modulator channels. For example, the term

ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given

are typical. Refer to the Electrical Characteristics for minimum and maximum values.

Calculations should be performed with tolerance values taken into consideration.

The bandgap cell common to both outputs, trimmed to 800 mV.

The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are

internally configured to operate on alternating switch cycles (that is, 180 ° out of phase).

When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and

all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises

above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup

sequence. If either output is enabled ( ENx pulled low), the BP regulator turns on, charging the BP capacitor with

a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start begins, depending on the

SEQ mode of operation and the EN1 and EN2 settings.

Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be

higher or lower than PVDD2. (See the Dual Supply Operation section.)

Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to

PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the

associated output is enabled and soft start is initiated.

If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is

shut down and minimal functions are active. The total standby current from both PVDD pins is approximately

70 µ A at 12-V input supply.

Product Folder Link(s): TPS54283 TPS54286