Datasheet
TPS54262-Q1
www.ti.com
SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010
DC ELECTRICAL CHARACTERISTICS
VIN = 7 V to 48 V, EN = VIN, T
J
= –40°C to 150°C (unless otherwise noted)
TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE (EN)
PT V
IL
Low input threshold voltage 0.7 V
PT V
IH
High input threshold voltage 1.7 V
EN = 60 V 100 135 µA
PT I
lkg
Leakage current into EN terminal
EN = 12 V 8 15 µA
RESET DELAY (Cdly)
PT I
O
External capacitor charge current EN = high 1.4 2 2.6 µA
PT V
Threshold
Switching threshold voltage Output voltage in regulation 2 V
LOW-POWER MODE (LPM)
PT V
IL
Low input threshold voltage VIN = 12 V 0.7 V
PT V
IH
High input threshold voltage VIN = 12 V 1.7 V
PT I
lkg
Leakage current into LPM terminal LPM = 5 V 65 95 µA
RESET OUTPUT (RST)
PT t
rdly
POR delay timer Based on Cdly capacitor 3.6 7 ms/nF
PT VReg_RST Reset threshold voltage for V
Reg
Check RST output 0.768 0.832 V
PT t
nRSTdly
Filter time Delay before RST is asserted low 10 20 35 µs
SOFT START (SS)
PT I
SS
Soft-start source current 40 50 60 µA
SYNCHRONIZATION (SYNC)
PT V
IL
Low input threshold voltage 0.7 V
PT V
IH
High input threshold voltage 1.7 V
PT I
lkg
Leakage current SYNC = 5 V 65 95 µA
VIN = 12 V, V
Reg
= 5 V,
CT SYNC (f
ext
) External input clock frequency 180 2200 kHz
180 kHz < f
sw
< f
ext
< 2 × f
sw
< 2.2 MHz
Info SYNC
trans
External clock to internal clock No external clock, VIN = 12 V, V
Reg
= 5 V 32 µs
External clock = 1 MHz, VIN = 12 V,
Info SYNC
trans
Internal clock to external clock 2.5 µs
V
Reg
= 5 V
CT SYNC
CLK
Minimum duty cycle 30 %
CT SYNC
CLK
Maximum duty cycle 70 %
Rslew
CT I
Rslew
Rslew = 50 kΩ 20 µA
CT I
Rslew
Rslew = 10 kΩ 100 µA
OVERVOLTAGE SUPERVISORS (OV_TH)
Threshold voltage for V
Reg
during
Internal switch is turned off 0.768 0.832 V
overvoltage
PT VReg_OV
V
Reg
= 5 V Internal pulldown on V
Reg
, OV_TH = 1 V 70
(1)
mA
THERMAL SHUTDOWN
Thermal shutdown junction
CT T
SD
175 °C
temperature
CT T
HYS
Hysteresis 30 °C
PT: Production tested
CT: Characterization tested only, not production tested
(1) This is the current flowing into the VReg pin when voltage at OV_TH pin is 1 V.
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