Datasheet

TPS54262-Q1
SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010 www.ti.com
Thermal Shutdown (TSD)
The TPS54262 protects itself from overheating with an internal thermal shutdown (TSD) circuit. If the junction
temperature exceeds the thermal shutdown trip point, the NMOS switching FET is turned off. The device is
automatically restarted under the control of soft-start circuit when the junction temperature drops below the
thermal shutdown hysteretic trip point. During low-power mode operation, the thermal shutdown sensing circuitry
is disabled for reduced current consumption. If V
Reg
drops below VReg_UV, thermal shutdown monitoring is
activated.
Overcurrent Protection
The device features overcurrent protection to protect it from load currents greater than 2 A. Overcurrent
protection is implemented by sensing the current through the NMOS switching FET. The sensed current is
compared to a current reference level representing the overcurrent threshold limit (I
CL
). If the sensed current
exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the
overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise
glitches.
Once overcurrent indicator is set true, overcurrent protection is triggered. The NMOS switching FET is turned off
for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle
current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature
of the part will start rising, the TSD will kick in and shut down switching until the part cools down.
Internal Undervoltage Lockout (UVLO)
This device is enabled on power up once the internal bandgap and bias currents are stable; this happens
typically at VIN = 3.4 V (minimum). On power down, the internal circuitry is disabled at VIN = 2.6 V (maximum).
Power Dissipation and Temperature Considerations
The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power
dissipated by the device is the sum of the following power losses.
Conduction losses, P
CON
(25)
Switching losses, P
SW
(26)
Gate drive losses, P
Gate
P
Gate
= V
drive
× Q
g
× f
sw
(27) (27)
Power supply losses, P
IC
P
IC
= VIN × I
q-Normal
(28) (28)
Therefore, the total power dissipated by the device is given by Equation 29.
P
Total
= P
CON
+ P
SW
+ P
Gate
+ P
IC
(29) (29)
Where,
VIN = unregulated input voltage
I
Load
= output load current
t
r
= FET switching rise time (t
r
= 40 ns (maximum))
t
f
= FET switching fall time
f
sw
= switching frequency
V
drive
= FET gate drive voltage (V
drive
= 6 V (typical), V
drive
= 8 V (maximum))
Q
g
= 1×10
-9
C
I
q-Normal
= quiescent current in normal mode (Active Mode CCM)
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