Datasheet

VReg_RST
VIN
VReg
Cdly
RST
t
delay
Css
VIN
VReg
Cdly
RST
Css
VReg_RST
20 s
(Typ-DeglitchTime)
m
TPS54262-Q1
SLVS996C –SEPTEMBER 2009–REVISED JUNE 2010 www.ti.com
Power On Condition/ Reset Line Power Down Condition/ Reset Line
Figure 26. Figure 27.
Reset Delay
The delay time to assert the RST pin high after the supply has exceeded the programmed VReg_RST voltage
(see Equation 11 to calculate VReg_RST) can be set by external capacitor (C2 in Figure 4) connected to the
Cdly pin (pin 9). The delay may be programmed in the range of 2.2 ms to 200 ms using a capacitor in the range
of 2.2 nF to 200 nF. The delay time is calculated using Equation 9:
(9)
Where,
C = capacitor on Cdly pin
Reset Threshold and Undervoltage Threshold
The undervoltage threshold (VReg_UV) level for proper regulation in low-power mode and the reset threshold
level (VReg_RST) to initiate a reset output signal can be programmed by connecting an external resistor string to
the RST_TH pin (pin 13). The resistor combination of R1, R2, and R3 is used to program the threshold for
detection of undervoltage. Voltage bias on R2 + R3 sets the reset threshold.
Undervoltage threshold for transient and low-power mode operation is given by the Equation 10. The
recommended range for VReg_UV is 73% to 95% of V
Reg
.
(10)
Reset threshold is given by Equation 11. The recommended range for VReg_RST is 70% to 92% of V
Reg
.
(11)
20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54262-Q1