Datasheet

BOOT
VSENSE
PH
VIN
GND
EN
Vout
PH
Vin
TOPSIDE
GROUND
AREA
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
CATCH
DIODE
SignalVIA
RouteBOOT CAPACITOR
traceonotherlayertoprovide
widepathfortopsideground
RESISTOR
DIVIDER
Feedback Trace
COMP
SS
COMPENSATION
NETWORK
ThermalVIA
SLOWSTART
CAPACITOR
UVLO
RESISTOR
DIVIDER
TPS54233
SLUS859B –OCTOBER 2008– REVISED FEBRUARY 2011 www.ti.com
Figure 13. TPS54233 Board Layout
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 12 is 0.72 in
2
. This area
does not include test points or connectors.
ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54233 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Step by Step Design Procedure above to prevent potential EMI issues.
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Product Folder Link(s): TPS54233