Datasheet

-0.025
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
0.025
5 6 7 8 9 10 11 12 13 14 15
V -InputVoltage-V
I
I =1 A
O
OutputRegulation-%
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
I -OutputCurrent- A
O
OutputVoltageRegulation-%
V =5V
I
V =12V
I
V =15V
I
V =3.3V
O
60
65
70
75
80
85
90
95
100
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
I -OutputCurrent- A
O
Efficiency-%
V =5V
I
V =12V
I
V =15V
I
50
55
60
65
70
75
80
85
90
95
100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Efficiency - %
V = 8 V
I
V = 12 V
I
V = 15 V
I
I - Output Current - A
O
TPS54232
SLVS876C –NOVEMBER 2008–REVISED OCTOBER 2013 www.ti.com
ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54232 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Step by Step Design Procedure above to prevent potential EMI issues.
APPLICATION CURVES
space
Figure 14. TPS54232 Efficiency Figure 15. TPS54232 Low Current Efficiency
Figure 16. TPS54232 Load Regulation Figure 17. TPS54232 Line Regulation
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Product Folder Links: TPS54232