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VIN

GND

BOOT

VSENSE

COMP

VIN

VOUT

TPS54232

BOOT

Ren1

Ren2

V =3.3V

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

I -OutputCurrent- A

V =5V

V =12V

V =15V

100

Efficiency-%

TPS54232

www.ti.com

SLVS876C –NOVEMBER 2008–REVISED OCTOBER 2013

2A, 28V, 1MHz, STEP DOWN DC/DC CONVERTER WITH ECO-MODE™

Check for Samples: TPS54232

FEATURES

APPLICATIONS

• 3.5 V to 28 V Input Voltage Range

• Consumer Applications such as Set-Top

Boxes, CPE Equipment, LCD Displays,

• Adjustable Output Voltage Down to 0.8 V

Peripherals, and Battery Chargers

• Integrated 80 mΩ High Side MOSFET Supports

• Industrial and Car Audio Power Supplies

up to 2 A Continuous Output Current

• 5V, 12V and 24V Distributed Power Systems

• High Efficiency at Light Loads with a Pulse

Skipping Eco-mode™

DESCRIPTION

• Fixed 1 MHz Switching Frequency

The TPS54232 is a 28 V, non-synchronous buck

• Typical 1 μA Shutdown Quiescent Current

converter that integrates a low R

DS(on)

high side

• Adjustable Slow Start Limits Inrush Currents

MOSFET. To increase efficiency at light loads, a

pulse skipping Eco-mode™ feature is automatically

• Programmable UVLO Threshold

activated. Furthermore, the 1 μA shutdown supply

• Overvoltage Transient Protection

current allows the device to be used in battery

• Cycle-by-Cycle Current Limit, Frequency Fold

powered applications. Current mode control with

Back and Thermal Shutdown Protection

internal slope compensation simplifies the external

compensation calculations and reduces component

• Available in 8-Pin SOIC Package

count while allowing the use of ceramic output

• Supported by SwitcherPro™ Software Tool

capacitors. A resistor divider programs the hysteresis

(http://focus.ti.com/docs/toolsw/folders/print/s

of the input under-voltage lockout. An overvoltage

witcherpro.html)

transient protection circuit limits voltage overshoots

during startup and transient conditions. A cycle by

cycle current limit scheme, frequency fold back and

thermal shutdown protect the device and the load in

the event of an overload condition. The TPS54232 is

available in an 8-pin SOIC package.

SIMPLIFIED SCHEMATIC EFFICIENCY

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-mode, SwitcherPro, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 2A, 28V, 1MHz, STEP DOWN DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54232 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • • 3.5 V to 28 V Input Voltage Range Adjustable Output Voltage Down to 0.
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TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED For additional design needs, see: TPS54231 TPS54232 TPS54233 TPS54331 IO(Max) 2A 2A 2A 3A TPS54332 3.5A Input Voltage Range 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V Switching Freq.
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TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 PACKAGE DISSIPATION RATINGS (1) (1) (2) (3) (2) (3) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT PSEUDO THERMAL IMPEDANCE JUNCTION TO TOP D 100°C/W 5°C/W Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase.
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TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted) DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal Shutdown 165 °C SLOW START (SS PIN) Charge current V(SS) = 0.4 V 2 μA SS to VSENSE matching V(SS) = 0.
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TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 FUNCTIONAL BLOCK DIAGRAM EN VIN 165 C Thermal Shutdown 1 mA 3 mA Shutdown Shutdown Logic 1.25 V Enable Threshold Enable Comparator Boot Charge ™ ECO-MODE Minimum Clamp Boot UVLO BOOT 2.1V Error Amplifier VSENSE 2 mA Gate Drive Logic gm = 92 mA/V DC gain = 800 V/V BW = 2.7 MHz Voltage Reference SS 2 kW 0.
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TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.8240 0.8120 0.8060 0.8000 0.7940 0.7880 0.7820 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 VIN = 12 V 130 120 110 -25 0 Figure 4. 25 50 75 100 TJ - Junction Temperature - °C 125 2.05 5.0 Current Limit Threshold - A ISS - Slow Start Charge Current - mA 11.5 11.0 10.5 10.0 9.
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TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 OVERVIEW The TPS54232 is a 28 V, 2 A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54232 has a pre-set switching frequency of 1MHz. The TPS54232 needs a minimum input voltage of 3.
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TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com ENABLE AND ADJUSTABLE INPUT UNDER-VOLTAGE LOCKOUT (VIN UVLO) The EN pin has an internal pull-up current source that provides the default condition of the TPS54232 operating when the EN pin floats. The TPS54232 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add hysteresis unless VIN is greater than (VOUT + 2V).
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TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 CURRENT MODE COMPENSATION DESIGN To simplify design efforts using the TPS54232, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases.
PAGE 10
TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION Figure 12. Typical Application Schematic STEP BY STEP DESIGN PROCEDURE The following design procedure can be used to select component values for the TPS54232. Alternately, the SwitcherPro™Software may be used to generate a complete design. The SwitcherPro™ Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design.
PAGE 11
TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 OUTPUT VOLTAGE SET POINT The output voltage of the TPS54232 is externally adjustable using a resistor divider network. In the application circuit of Figure 12, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5: R5 ´ VREF R6 = VOUT - VREF (4) é R5 ù VOUT = VREF ´ ê +1ú ë R6 û (5) Choose R5 to be approximately 10 kΩ.
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TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 LMIN = VOUT(MAX) ´ www.ti.com (VIN(MAX) - VOUT ) VIN(MAX) ´ KIND ´ IOUT ´ FSW (8) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.4 may be used.
PAGE 13
TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 The maximum ESR of the output capacitor can be determined from the amount of allowable output ripple as specified in the initial design parameters. The contribution to the output ripple voltage due to ESR is the inductor ripple current times the ESR of the output filter, so the maximum specified ESR as listed in the capacitor data sheet is given by Equation 13 ESRmax = VOPPMAX ILPP - (D - 0.
PAGE 14
TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com Gain = - 20 log (2 ´ p ´ RSENSE ´ FCO ´ CO ) - 2dB (19) Where: RSENSE = 1Ω/10 FCO = Closed-loop crossover frequency CO = Output capacitance The phase loss is given by Equation 20: PL = a tan (2 ´ p ´ FCO ´ RESR ´ CO ) - a tan (2 ´ p ´ FCO ´ RO ´ CO ) - 10deg (20) Where: RESR = Equivalent series resistance of the output capacitor RO = VO/IO The measured overall loop response for the circuit is given in Figure 20.
PAGE 15
TPS54232 www.ti.com CZ = CP = SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 1 2 ´ p ´ FZ 1 ´ Rz (26) 1 2 ´ p ´ FP1 ´ Rz (27) For this design, a 22 μF output capacitor issued. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a dc bias voltage applied. This is the case in a dc/dc converter. For this design, a 10 V capacitor is chosen to minimize this effect. The ESR is approximately 0.005 Ω.
PAGE 16
TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com OUTPUT VOLTAGE LIMITATIONS Due to the internal design of the TPS54232, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 90% and is given by Equation 31: VOmax = 0.
PAGE 17
TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C). PCB LAYOUT The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode.
PAGE 18
TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS As EMI becomes a rising concern in more and more applications, the internal design of the TPS54232 takes measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used to lower the parasitics effects.
PAGE 19
TPS54232 www.ti.com SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 60 180 50 150 VOUT Gain 40 120 30 90 Phase IOUT 0.5 - 2 A STEP 60 10 30 0 0 Phase - Deg. Gain - dB 20 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 t - Time - 2 ms/div -60 10 Figure 18. TPS54232 Transient Response 100 1k 10k f - Frequency - Hz 100k -180 1M Figure 19. TPS54232 Loop Response VOUT VIN PH PH t - Time - 1 ms/div t - Time - 1 ms/div Figure 20. TPS54232 Output Ripple Figure 21.
PAGE 20
TPS54232 SLVS876C – NOVEMBER 2008 – REVISED OCTOBER 2013 www.ti.com VOUT VOUT VIN SS t - Time - 2 ms/div t - Time - 2 ms/div Figure 22. TPS54232 Start Up Figure 23. TPS54232 Start-up Relative to Enable REVISION HISTORY Changes from Original (November 2008) to Revision A Page • Added a new table to the Description - For additional design needs ...................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.