Datasheet

TPS54227
SLVSAU2B –MAY 2011–REVISED JUNE 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
TRANSPORT
T
A
PACKAGE
(2) (3)
ORDERABLE PART NUMBER PIN
MEDIA
TPS54227DDA Tube
DDA 8
TPS54227DDAR Tape and Reel
–40°C to 85°C
TPS54227DRCT
DRC 10 Tape and Reel
TPS54227DRCR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN MAX
VIN, EN –0.3 20 V
VBST –0.3 26 V
VBST (10 ns transient) –0.3 28 V
Input voltage range VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5 V
SW –2 20 V
SW (10 ns transient) –3 22 V
VREG5 –0.3 6.5 V
Output voltage range
GND –0.3 0.3 V
Voltage from GND to thermal pad, V
diff
–0.2 0.2 V
Human Body Model (HBM) 2 kV
Electrostatic discharge
Charged Device Model (CDM) 500 V
Operating junction temperature, T
J
–40 150 °C
Storage temperature, T
stg
–55 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS54227
THERMAL METRIC
(1)(2)
UNITS
DDA (8 PINS) DRC (10 PINS)
θ
JA
Junction-to-ambient thermal resistance 45.3 43.9
θ
JCtop
Junction-to-case (top) thermal resistance 54.8 55.4
θ
JB
Junction-to-board thermal resistance 16.2 18.9
°C/W
ψ
JT
Junction-to-top characterization parameter 6.6 0.7
ψ
JB
Junction-to-board characterization parameter 16.0 19.1
θ
JCbot
Junction-to-case (bottom) thermal resistance 8.5 5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2 Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS54227