Datasheet

ref
OUT ref
V
R7 = R6
V V-
-
×
- + × ´
6
STOP
1.18 R1
R2 =
V 1.18 R1 3.2 10
-
× -
´
START STOP
6
0.944 V V
R1 =
2.59 10
SS SS
SS
ref
T (mS) I ( A)
C (nF) =
V (V)
´ m
TPS54218
SLVS974B –SEPTEMBER 2009–REVISED JULY 2013 www.ti.com
Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3
sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steady-
state DC level of COMP must be measured at the minimum designed load and at the maximum designed input
voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions give the
minimum COMP voltage for a given design. Generally, the COMP voltage and minimum clamp voltage move by
about the same amount with temperature. Increasing the minimum load COMP voltage is accomplished by
decreasing the output inductor value or the switching frequency used in a given design.
SLOW START CAPACITOR
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54218 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start capacitor value can be calculated using Equation 28. For the example circuit, the slow start time is
not too critical since the output capacitor value is 44 μF which does not require much current to charge to 1.8 V.
The example circuit has the slow start time set to an arbitrary value of 4ms which requires a 10 nF capacitor. In
TPS54218, Iss is 2 μA and Vref is 0.8 V. TI recommends keeping the soft-start time in the range of 1 to 10 ms.
(28)
BOOTSTRAP CAPACITOR SELECTION
A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
UNDERVOLTAGE LOCK OUT SET POINT
The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54218. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 3.1 V (V
START
). After the regulator starts switching, it should
continue to do so until the input voltage falls below 2.8 V (V
STOP
).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 29 and Equation 30 can be used to calculate the resistance values necessary. From Equation 29
and Equation 30, a 48.7 kΩ between Vin and EN and a 32.4 kΩ between EN and ground are required to produce
the 3.1 and 2.8 volt start and stop voltages.
(29)
(30)
OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION
For the example design, 100 kΩ was selected for R6. Using Equation 31, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.5 kΩ.
(31)
Due to the internal design of the TPS54218, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 32
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