Datasheet
OUT
IN
IN
I max 0.25
V =
C sw
´
D
´ ¦
( )
IN OUT
OUT
OUT
IN IN
V min V
V
Icirms = I
V min V min
-
´ ´
OUT IN OUT
IN
V (V max V )
Icorms =
12 V max L1 sw
´ -
´ ´ ´ ¦
Oripple
ESR
ripple
V
R <
I
TPS54218
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SLVS974B –SEPTEMBER 2009–REVISED JULY 2013
Where ΔI
OUT
is the change in output current, Fsw is the regulators switching frequency and ΔV
OUT
is the
allowable change in the output voltage. (23)
Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 24 indicates the ESR should be less than 57 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 57 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22 μF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields
151mA.
(24)
(25)
INPUT CAPACITOR
The TPS54218 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54218.
The input ripple current can be calculated using Equation 26.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 27. Using the design example values, I
OUT
max = 2 A, C
IN
= 10 μF,
Fsw = 1 MHz, yields an input voltage ripple of 34 mV and a rms input ripple current of 0.98 A.
(26)
(27)
COMP VOLTAGE LEVEL
The TPS54218 implements a minimum COMP voltage clamp for improved load-transient response. The COMP
voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreases as the
peak inductor current decreases. During a severe load-dump event, for instance, the COMP voltage decreases
suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop
compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turnon of
the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage
overshoot more quickly.
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