Datasheet

SYNCClock=2V/div

PH=2V/div

Time=500nsec/div

TPS54218

Clock

Source

PLL

RT/CLK

TPS54218

www.ti.com

SLVS974B –SEPTEMBER 2009–REVISED JULY 2013

REVERSE OVERCURRENT PROTECTION

The TPS54218 implements low side current protection by detecting the voltage across the low side MOSFET.

When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if

the reverse current is more than 1.3 A. By implementing this additional protection scheme, the converter is able

to protect itself from excessive current during power cycling and start-up into pre-biased outputs.

SYNCHRONIZE USING THE RT/CLK PIN

The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement

the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least

75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a

synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the

internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set

by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V

typically. The recommended synchronization frequency range is 300 kHz to 2000 kHz. If the external system

clock is to be removed, TI recommends that it be removed on the falling edge of the clock.

Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock

POWER GOOD (PWRGD PIN)

The PWRGD pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage enters

the fault condition by falling below 91% or rising above 107% of the nominal internal reference voltage. There is

a 2% hysteresis on the threshold voltage, so when the VSENSE voltage rises to the good condition above 93%

or falls below 105% of the internal voltage reference the PWRGD output MOSFET is turned off. It is

recommended to use a pull-up resistor between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or

less. The PWRGD is in a valid state once the VIN input voltage is greater than 1.2 V.

OVERVOLTAGE TRANSIENT PROTECTION

The TPS54218 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot

when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output

overshoot by implementing a circuit to compare the VSENSE pin voltage to the OVTP threshold which is 109%

of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side

MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the

VSENSE voltage drops lower than the OVTP threshold the high side MOSFET is allowed to turn on the next

clock cycle.

THERMAL SHUTDOWN

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C.

The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal

trip threshold. Once the die temperature decreases below 160°C, the device reinitiates the power up sequence

by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C.

Product Folder Links :TPS54218