Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder WQFN 16

100

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

I -OutputCurrent- A

Efficiency-%

V =5V,

V =1.8V,

F =1000kHz

VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54218

RT /CLK

PWRGD

BOOT

VOUT

VIN

AGND

GND

TPS54218

www.ti.com

SLVS974B –SEPTEMBER 2009–REVISED JULY 2013

2.95 V to 6 V Input, 2 A Output, 2MHz, Synchronous Step Down

Switcher With Integrated FETs ( SWIFT™)

Check for Samples: TPS54218

FEATURES

DESCRIPTION

The TPS54218 device is a full featured 6 V, 2 A,

• Two 30 mΩ (typical) MOSFETs for High

synchronous step down current mode converter with

Efficiency at 2 A loads

two integrated MOSFETs.

• 200kHz to 2MHz Switching Frequency

The TPS54218 enables small designs by integrating

• 0.8 V ± 1% Voltage Reference Over

the MOSFETs, implementing current mode control to

Temperature

reduce external component count, reducing inductor

• Synchronizes to External Clock

size by enabling up to 2 MHz switching frequency,

and minimizing the IC footprint with a small 3mm x

• Adjustable Slow Start/Sequencing

3mm thermally enhanced QFN package.

• UV and OV Power Good Output

The TPS54218 provides accurate regulation for a

• Low Operating and Shutdown Quiescent

variety of loads with an accurate ±1% Voltage

Current

Reference (V

ref

) over temperature.

• Safe Start-up into Pre-Biased Output

Efficiency is maximized through the integrated 30mΩ

• Cycle by Cycle Current Limit, Thermal and

MOSFETs and 350μA typical supply current. Using

Frequency Fold Back Protection

the enable pin, shutdown supply current is reduced to

• –40°C to 150°C Operating Junction

2 μA by entering a shutdown mode.

Temperature Range

Undervoltage lockout is internally set at 2.6 V, but

• Thermally Enhanced 3mm × 3mm 16-pin QFN

can be increased by programming the threshold with

a resistor network on the enable pin. The output

APPLICATIONS

voltage startup ramp is controlled by the slow start

pin. An open drain power good signal indicates the

• Low-Voltage, High-Density Power Systems

output is within 93% to 107% of its nominal voltage.

• Point of Load Regulation for High Performance

Frequency fold back and thermal shutdown protects

DSPs, FPGAs, ASICs and Microprocessors

the device during an overcurrent condition.

• Broadband, Networking and Optical

Communications Infrastructure

The TPS54218 is supported in the SwitcherPro

Software Tool at www.ti.com/switcherpro.

SIMPLIFIED SCHEMATIC

For more SWIFT

documentation, see the TI

website at www.ti.com/swift.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 2.95 V to 6 V Input, 2 A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™) Check for Samples: TPS54218 FEATURES DESCRIPTION • The TPS54218 device is a full featured 6 V, 2 A, synchronous step down current mode converter with two integrated MOSFETs. 1 2 • • • • • • • • • • Two 30 mΩ (typical) MOSFETs for High Efficiency at 2 A loads 200kHz to 2MHz Switching Frequency 0.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ PACKAGE –40°C to 150°C 3 × 3 mm QFN PART NUMBER (1) TPS54218RTET TPS54218RTER The RTE package is only available taped and reeled.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 2.6 2.8 V 2 5 μA 350 500 μA 1.25 1.37 V SUPPLY VOLTAGE (VIN PIN) Operating input voltage 2.95 Internal under voltage lockout threshold No voltage hysteresis, rising and falling Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V Quiescent Current - Iq VSENSE = 0.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT BOOT (BOOT PIN) BOOT Charge Resistance VIN = 5 V 16 Ω BOOT-PH UVLO VIN = 2.95 V 2.1 V Charge Current V(SS) = 0.4 V 1.8 μA SS to reference crossover 98% nominal 0.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 PIN CONFIGURATION 2 GND 3 GND 4 EN PWRGD BOOT 14 13 Thermal Pad (17) AGND 5 6 7 8 RT/CLK VIN 15 COMP 1 16 VSENSE VIN VIN QFN16 RTE PACKAGE (TOP VIEW) 12 PH 11 PH 10 PH 9 SS PIN FUNCTIONS PIN DESCRIPTION NAME NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH.
PAGE 6
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 TYPICAL CHARACTERISTICS CURVES FREQUENCY vs TEMPERATURE 550 High Side Rdson VI = 3.3 V Low Side Rdson VI = 3.3 V 0.05 0.045 540 fs - Switching Frequency - kHz RDSON - Static Drain-Source On-State Resistance - W HIGH SIDE AND LOW SIDE RDS (on) vs TEMPERATURE 0.055 High Side Rdson VI = 5 V 0.04 0.035 Low Side Rdson VI = 5 V 0.03 RT = 400 kW, VI = 3.3 V 530 520 510 500 490 480 470 0.025 460 0.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SWITCHING FREQUENCY vs VSENSE TRANSCONDUCTANCE vs TEMPERATURE 100 280 VIN = 3 .3 V 260 EA - Transconductance - mA/V Normal Switching Frequency - % Vsense Falling 75 Vsense Rising 50 25 240 220 200 180 160 0 0 0.1 0.2 0.3 0.4 0.5 Vsense - V 0.6 0.7 140 -50 0.8 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 7. 150 Figure 8.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 TYPICAL CHARACTERISTICS CURVES (continued) CHARGE CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE -1 105 -1.2 103 SS/TR - Discharge Current - mA SS/TR - Charge Current - mA -1.4 VIN = 5 V -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 101 VIN = 5 V 99 97 95 93 91 89 87 -3 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 85 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 13. 150 Figure 14.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE 110 400 390 108 380 106 PWRGD - Threshold - % Vref ICC - Supply Current - mA TJ = 25°C 370 360 350 340 330 Vsense Falling 104 102 100 98 96 94 320 Vsense Rising 92 310 90 300 88 -50 3 3.5 4 4.5 5 VIN - Input Voltage - V 5.5 6 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 20.
PAGE 11
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 The TPS54218 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54218 to operate approaching 100%.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com VOLTAGE REFERENCE The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier. ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin.
PAGE 13
TPS54218 www.ti.com R1 = R2 = SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 0.944 × VSTART - VSTOP 2.59 ´ 10-6 (2) 1.18 × R1 VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6 (3) SLOW START PIN The TPS54218 regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the SS pin to ground implements a slow start-time. The TPS54218 has an internal pull-up current source of 1.8μA which charges the external slow start capacitor.
PAGE 14
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com TPS54218 EN1 = 2 V / div EN SS Vout1 = 1 V / div PWRGD Vout2 = 1 V / div TPS54218 EN Time = 5 msec / div SS PWRGD Figure 27. Schematic for Ratiometric Start-Up Sequence Figure 28.
PAGE 15
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 REVERSE OVERCURRENT PROTECTION The TPS54218 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is more than 1.3 A.
PAGE 16
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com SMALL SIGNAL MODEL FOR LOOP RESPONSE Figure 31 shows an equivalent model for the TPS54218 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 225 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 VO Adc VC RESR fp RL gmps COUT fz Figure 32.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com The design guidelines for TPS54218 loop compensation are as follows: 1. The modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 11 and Equation 12. Derating the output capacitor (COUT) may be needed if the output voltage is a high percentage of the capacitor rating. Use the capacitor manufacturer information to derate the capacitor value.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA511 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
PAGE 20
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com For this design example, use KIND = 0.3 and the inductor value is calculated to be 2.10 μH. For this design, a nearest standard value was chosen: 2.2 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 20 and Equation 21. For this design, the RMS inductor current is 2 A and the peak inductor current is 2.3 A.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 Where ΔIOUT is the change in output current, Fsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. (23) Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 57 mΩ. In this case, the ESR of the ceramic capacitor is much less than 57 mΩ.
PAGE 22
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3 sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steadystate DC level of COMP must be measured at the minimum designed load and at the maximum designed input voltage, then compared to the minimum COMP clamp voltage shown in Figure 22.
PAGE 23
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 ( ( )))- (IOUTmin ´ (RL + RDS )) ( VOUT min = Ontimemin ´ FSmax ´ VINmax - IOUT min ´ (2 ´ RDS ) Where: VOUTmin = minimum achievable output voltage Ontimemin = minimum controllable on-time (60 ns typical.
PAGE 24
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 R3 = www.ti.com 2p × ¦ c ´ VOUT ´ COUT gm ´ Vref ´ VIgm (38) 2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 39. ´ COUT R C3 = OUT R3 (39) 3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it. From the procedures above, the compensation network includes a 9.
PAGE 25
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 POWER UP VOUT, VIN POWER DOWN VOUT, VIN VI = 2 V/div VI = 2 V/div EN = 1 V/div EN = 1 V/div SS = 1 V/div SS = 1 V/div VO = 1 V/div VO = 1 V/div Time = 5 ms/div Time = 500 ms/div Figure 39. Figure 40. POWER UP VOUT, EN VI = 2 V/div POWER DOWN VOUT, EN VI = 2 V/div EN = 1 V/div EN = 1 V/div SS = 1 V/div SS = 1 V/div VO = 1 V/div VO = 1 V/div Time = 500 ms/div Time = 5 ms/div Figure 41. Figure 42.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com INPUT RIPPLE, 0 A INPUT RIPPLE, 2 A VI = 50 mV/div (ac coupled) VI = 10 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 45. Figure 46. LOAD REGULATION vs LOAD CURRENT CLOSED LOOP RESPONSE, VIN (3.3 V), 2 A 60 0.25 180 0.2 Fhase Output Voltage Change - % 0.15 Gain Phase Gain 0.1 0.05 VI = 3.3 V 0 -0.05 -0.1 -0.15 -0.2 -60 10 -180 1M f - Frequency - Hz -0.25 0 0.25 0.
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TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq). Pcon = IOUT 2 × RDS(on) Pd = ƒsw × IOUT × 0.7 × 60 × 10-9 Psw = 2 × VIN 2 × ƒsw × IOUT × 0.
PAGE 28
TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com TAmax - Maximum Ambient Temperature - °C 150 140 130 120 TJmax = 150°C, no air flow 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 PD - Power Dissipated - W 3 3.5 Figure 52. Maximum Ambient Temperature vs IC power Dissipation LAYOUT Layout is a critical portion of good power supply design.
PAGE 29
TPS54218 www.ti.com SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 VIA to Ground Plane UVLO SET RESISTRORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT/CLK COMP VSENSE AGND SS FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA VIA to Ground Plane Figure 53.
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TPS54218 SLVS974B – SEPTEMBER 2009 – REVISED JULY 2013 www.ti.com REVISION HISTORY Changes from Original (September 2009) to Revision A • Page Added "Instantaneous peak current" to the Current Limit in the Electrical Characteristics table ......................................... 3 Changes from Revision A (September 2009) to Revision B Page • Added Minimum Comp Voltage Clamp vs Temperature graph to TYPICAL CHARACTERISTIC CURVES .....................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54218RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54218RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54218RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54218RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54218RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54218RTET WQFN RTE 16 250 210.0 185.0 35.
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