Datasheet
Fp1=500000 ×
V
O
F
LC
(15)
Fz1=0.7 F
LC
×
(16)
Fz2=2.5×F
LC
(17)
C7=
1
2 Fp1 (R1||R2)π × ×
(18)
R3=
1
2 ×Fz1×C7π
(19)
C6=
1
2 ×Fz2×R1π
(20)
ADVANCED INFORMATION
Output Voltage Limitations
V
OUTMAX
+ 0.87
ǒǒ
V
INMIN
* I
OMAX
0.230
Ǔ
) V
D
Ǔ
*
ǒ
I
OMAX
R
L
Ǔ
* V
D
(21)
TPS5420-Q1
SLVS752B – NOVEMBER 2007 – REVISED JUNE 2008 ...................................................................................................................................................
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The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor the
overall response of the feedback network to accommodate the use of the ceramic output capacitors. The pole
and zero locations are given by the following equations:
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by
Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.
Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as
calculated usingEquation 12 . For this design R1 = 10 k Ω and R2 = 5.90 k Ω . With Fp1 = 426 Hz, Fz1 = 2708 Hz
and Fz2 = 8898 Hz, the values of R3, C6 and C7 are determined using Equation 18 , Equation 19 , and
Equation 20 :
For this design, using the closest standard values, C7 is 0.1 µ F, R3 is 590 Ω , and C6 is 1800 pF. C5 is added to
improve load regulation performance. It is effectively in parallel with C6 in the location of the second pole
frequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For this
example, 150 pF works well.
For additional information on external compensation of the TPS5420 or other wide voltage range SWIFT devices,
see Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors (TI literature number SLVA237 ).
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
Where:
V
INMIN
is the minimum input voltage.
I
OMAX
is the maximum load current.
V
D
is the catch diode forward voltage.
R
L
is the output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
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