Datasheet

1
2
3
4
8
7
6
5
BOOT
NC
NC
VSENSE
PH
VIN
GND
ENA
TPS5420
SLVS642E –APRIL 2006–REVISED SEPTEMBER 2013 www.ti.com
PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin.
NC 2, 3 Not connected internally.
VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider.
ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND 6 Ground.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic
VIN 7
capacitor.
PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.
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