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VIN

ENA

GND

VSENSE

BOOT

TPS5420

VIN VOUT

100

0 0.5

1.5 2.5 3

Efficiency − %

I OutputCurrent A

EfficiencyvsOutputCurrent

SimplifiedSchematic

=12V

TPS5420

www.ti.com

SLVS642E –APRIL 2006–REVISED SEPTEMBER 2013

2-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER

Check for Samples: TPS5420

FEATURES

APPLICATIONS

• Wide Input Voltage Range: 5.5 V to 36 V • Consumer: Set-top Box, DVD, LCD Displays

• Up to 2-A Continuous (3-A Peak) Output • Industrial and Car Audio Power Supplies

Current

• Battery Chargers, High Power LED Supply

• High Efficiency up to 95% Enabled by 110-mΩ

• 12-V/24-V Distributed Power Systems

Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down DESCRIPTION

to 1.22 V with 1.5% Initial Accuracy

The TPS5420 is a high-output-current PWM

converter that integrates a low resistance high side

• Internal Compensation Minimizes External

N-channel MOSFET. Included on the substrate with

Parts Count

the listed features is a high performance voltage error

• Fixed 500-kHz Switching Frequency for Small

amplifier that provides tight voltage regulation

Filter Size

accuracy under transient conditions; an undervoltage-

• Improved Line Regulation and Transient

lockout circuit to prevent start-up until the input

voltage reaches 5.5 V; an internally set slow-start

Response by Input Voltage Feed Forward

circuit to limit inrush currents; and a voltage feed-

• System Protected by Over Current Limiting,

forward circuit to improve the transient response.

Over Voltage Protection and Thermal

Using the ENA pin, shutdown supply current is

Shutdown

reduced to 18 μA typically. Other features include an

• –40°C to 125°C Operating Junction

active-high enable, overcurrent limiting, overvoltage

Temperature Range

protection and thermal shutdown. To reduce design

complexity and external component count, the

• Available in Small 8-Pin SOIC Package

TPS5420 feedback loop is internally compensated.

The TPS5420 device is available in an easy to use 8-

pin SOIC package. TI provides evaluation modules

and the Designer software tool to aid in quickly

achieving high-performance power supply designs to

meet aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 2-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER Check for Samples: TPS5420 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • Wide Input Voltage Range: 5.5 V to 36 V Up to 2-A Continuous (3-A Peak) Output Current High Efficiency up to 95% Enabled by 110-mΩ Integrated MOSFET Switch Wide Output Voltage Range: Adjustable Down to 1.22 V with 1.
PAGE 2
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TJ INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE (1) PART NUMBER –40°C to 125°C 5.5 V to 36 V Adjustable to 1.
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TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI Input voltage range, VIN 5.5 36 V TJ Operating junction temperature –40 125 °C TYP MAX UNIT 3 4.4 mA 18 50 μA Start threshold voltage, UVLO 5.3 5.5 Hysteresis voltage, UVLO 330 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 5.
PAGE 4
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com PIN ASSIGNMENTS D PACKAGE (TOP VIEW) BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. BOOT 1 NC 2, 3 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. Not connected internally. VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.
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TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE OPERATING QUIESCENT CURRENT vs JUNCTION TEMPERATURE 530 f − Oscillator Frequency − kHz 510 500 490 480 470 460 -50 180 VI = 12 V 170 Minimum Controllable On Time − ns IQ − Operating Quiescent Current − mA 3.5 520 3.25 3 2.75 2.
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TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENABLE ENA SHDN SHDN VSENSE Z1 Thermal Protection NC SHDN VIN Ramp Generator NC SHDN VSENSE HICCUP PWM Comparator Overcurrent Protection Oscillator OVP Z2 Feed Forward Gain = 25 SHDN GND Error Amplifier SHDN SHDN Gate Drive Control 112.
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TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Undervoltage Lockout (UVLO) The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins.
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TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com Overvoltage Protection The TPS5420 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off.
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TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 PH BOOT CAPACITOR OUTPUT INDUCTOR RESISTOR DIVIDER VOUT BOOT PH NC VIN NC GND VSENSE ENA OUTPUT FILTER CAPACITOR Route feedback trace under the output filter capacitor or on the other layer. CATCH DIODE INPUT INPUT BULK BYPASS CAPACITOR FILTER Vin TOPSIDE GROUND AREA VIA to Ground Plane Signal VIA Figure 9.
PAGE 10
TPS5420 www.ti.com 0.050 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 0.026 0.220 0.080 All dimensions in inches Figure 10. TPS5420 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output current at a nominal output voltage of 5 V. U1 TPS5420D 10 V - 35 V 7 VIN ENA C1 4.7 mF C4 4.7 mF VIN 5 ENA 2 NC 3 NC 6 GND BOOT 1 C2 0.
PAGE 11
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Design Procedure The following design procedure can be used to select component values for the TPS5420. Alternately, the Designer Software may be used to generate a complete design. The Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.
PAGE 12
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com In this example, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1.0 A. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitors are rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin.
PAGE 13
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Capacitor Selection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist.
PAGE 14
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com For this design example, a single 100-μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is a AVX TPSD107M010R0080, rated at 10 V with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This capacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.
PAGE 15
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Circuit Using Ceramic Output Filter Capacitors Figure 13 shows an application circuit using all ceramic capacitors for the input and output filters which generates a 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design example, except for the selection of the output filter capacitor values and the design of the additional compensation components required to stabilize the circuit.
PAGE 16
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Fp1 = 500000 x www.ti.com VO FLC (15) Fz1 = 0.7 x FLC (16) Fz2 = 2.5 x FLC (17) The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower. Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as calculated usingEquation 12.
PAGE 17
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 Internal Compensation Network The design equations given in the example circuit can be used to generate circuits using the TPS5420. These designs are based on certain assumptions, and always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS5420.
PAGE 18
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com PERFORMANCE GRAPHS The performance graphs in Figure 14 - Figure 20 are applicable to the circuit in Figure 11. TA = 25°C. unless otherwise specified. 100 VI = 10.8 V 0.2 0.2 Output Regulation - % 90 85 VI = 18 V VI = 19.8 V 80 Output Regulation - % IO = 2 A VI = 15 V Efficiency - % 0.3 VI = 12 V 95 0.1 0 -0.1 -0.2 0 0.5 1 1.5 2 IO - Output Current - A 2.5 Figure 14. Efficiency vs.
PAGE 19
TPS5420 www.ti.com SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 VIN = 10 V/Div ENA = 2 V/Div VOUT = 2 V/Div VOUT = 2 V/Div t - Time = 5 ms/Div t - Time = 5 ms/Div Figure 20. Startup Waveform, VIN and VOUT Figure 21.
PAGE 20
TPS5420 SLVS642E – APRIL 2006 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (April 2006) to Revision A • Added Note 3 to the ABSOLUTE MAXIMUM RATINGS table ............................................................................................. 2 Changes from Revision A (August 2006) to Revision B • 20 Page Replaced the DISSIPATION RATINGS with the THERMAL INFORMATION table .............................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5420DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5420DR SOIC D 8 2500 367.0 367.0 35.
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