Datasheet

3 Board Layout
3.1 Layout
Board Layout www.ti.com
This section provides a description of the TPS54140EVM-429, board layout, and layer illustrations.
The board layout for the TPS54140EVM-429 is shown in Figure 11 through Figure 13 . The topside layer of
the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54140 and a large area filled with ground. The bottom layer
contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces
are connected with multiple vias placed around the board including ten vias directly under the TPS54140
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors (C2, and C3) and bootstrap capacitor (C6) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The voltage divider network ties to the output voltage at the point of regulation, the copper V
OUT
trace past
the output capacitor (C5). For the TPS54140, an additional input bulk capacitor may be required (C!),
depending on the EVM connection to the input supply.
Figure 11. TPS54140EVM-429 Top-Side Layout
10 TPS54140EVM-429 1.5-A, SWIFT™ Regulator Evaluation Module SLVU285 – March 2009
Submit Documentation Feedback