Datasheet

VSENSE

COMP

CO RO

97 A/Vm

0.8V

PowerStage

gm 6 A/V

ESR

OUT

TPS54140

www.ti.com

SLVS889B –OCTOBER 2008–REVISED SEPTEMBER 2013

DETAILED DESCRIPTION (continued)

Figure 46. Small Signal Model for Loop Response

Simple Small Signal Model for Peak Current Mode Control

Figure 47 describes a simple small signal model that can be used to understand how to design the frequency

compensation. The TPS54140 power stage can be approximated to a voltage-controlled current source (duty

cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer

function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient

of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage

transconductance. The gm

for the TPS54140 is 6A/V. The low-frequency gain of the power stage frequency

response is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the

load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of

Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB

crossover frequency the same for the varying load conditions which makes it easier to design the frequency

compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on

the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number

frequency compensation components needed to stabilize the overall loop because the phase margin increases

from the ESR zero at the lower frequencies (see Equation 17).

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