Datasheet

TPS54120

www.ti.com

SBVS180C –JANUARY 2012–REVISED JUNE 2012

PCB LAYOUT GUIDELINES

PACKAGE MOUNTING

Solder pad footprint recommendations for the TPS54120 are available at the end of this product datasheet and

at www.ti.com.

BOARD LAYOUT RECOMMENDATIONS FOR HIGH-PSR AND LOW-NOISE PERFORMANCE

Correct printed circuit board (PCB) layout is a critical portion of good power-supply design and is a particularly

important for the high PSR and low-noise performance of the TPS54120. The following general guidelines are

provided; for a more detailed description, refer to the TPS54120EVM User Guide, SLVU641.

• The inductor, the boot capacitor, and the output cap of the dc-dc converter should be placed on layers of the

board that help minimize the spread of the switching noise into the LDO area on the board, such as the

bottom layer.

• The boot cap and inductor L1 should be connected as close as possible to the PH pin to reduce parasitic

inductance of long traces.

• To help shield the compensation components, the soft-start capacitors, CLK/RT resistor, and dc-dc feedback

resistors from noise, these components should be grounded to a power ground that is shielded from the high-

current ground plane. This shielding can be achieved by using a separate trace to the PGND pin.

• The RT/CLK pin is sensitive to noise, so the RT resistor should be located as close as possible to the device

and routed with a short connection.

• The noise-reduction capacitor should be placed as close as possible to the device to avoid noise pickup into

the LDO reference.

• The ground planes on the input and the output should be isolated from each other and connected through a

separate trace route that parallels the power-loop routing from the dc-dc output to the LDO input.

• The low-noise analog ground of the LDO circuits (such as the voltage set point divider, the LDO input, and

output caps) should be terminated to ground using a wide ground trace separate from the power ground

plane.

• The LDO input capacitor and output capacitor should be as close to the device as possible.

• The VIN and PVIN pins must be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R

dielectric and placed as close as possible to the VIN, PVIN, and PGND pins.

• For operation at full-rated load, the top-side ground area together with the internal ground plane must provide

adequate heat dissipation.

• PCB conductor planes should be minimized to prevent excessive capacitive coupling.