Datasheet

TPS54120
SBVS180C –JANUARY 2012–REVISED JUNE 2012 www.ti.com
The internal LDO of the TPS54120 is designed to be stable with standard ceramic output capacitors with values
of 4.7 μF or larger; higher values are recommended for better noise performance.
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V
or higher voltage rating.
The output voltage of both the switcher and the LDO are adjustable using an external-resistor feedback network.
Also, both the LDO and the switcher have a soft-start function that can be adjusted externally using the C
SS
and
C
NR
capacitors, as shown in Figure 34.
There are several industry techniques used to compensate dc-dc regulators; refer to Application Report
SLVA503 for more details about different compensation networks for the TPS54120.
SIMPLIFIED DESIGN METHODOLOGY
The TPS54120 has a low-noise output voltage range of 0.8 V to 6.0 V with an output current of up to 1 A. To
simplify design efforts using the TPS54120, the typical designs for common applications are listed in Table 1. For
designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when
doing the stability analysis because the actual ceramic capacitance drops considerably from the nominal value
when the applied voltage increases. To execute a complete application design, refer to Application Report
SLVA506, Design Procedures for the TPS54120.
Table 1. Simplified Design Table
RMS NOISE
100 Hz
TO
DC-DC_ I
OUT
100 kHz
VIN OUT VOUT (max) f
SW
L
1
C
DC-DC_OUT
R
1
R
2
R
3
R
4
R
5
R
RT
C
1
C
2
C
OUT
C
11
C
FF
AT 100 mA EFFICIENCY
(V) (V) (V) (A) (kHz) (µH) (µF) (kΩ) (kΩ) (kΩ) (kΩ) (kΩ) (kΩ) (µF) (pF) (µF) (pF) (µF) (µVrms) (%)
5 3 1.8 1.0 480 18 47 27.4 10 1.58 12.4 10 100 0.047 330 100 270 0.1 7.32 56.35
7 2.5 1.8 0.25 300 100 47 21.5 10 0.887 12.4 10 165 0.220 1000 100 499 0.1 7.83 67.35
8 2.5 1.8 1.0 480 15 47 21.5 10 1.33 12.4 10 100 0.047 330 100 330 0.1 7.22 66.25
12 3.7 3.0 1.0 480 20 47 36.5 10 1.96 27.4 10 100 0.047 330 100 200 0.1 8.27 75.42
12 4.1 3.3 0.5 480 43 47 41.2 10 2.2 30.9 10 100 0.100 330 100 180 0.1 8.3 73.38
12 4.1 3.3 1.0 480 22 47 41.2 10 2.2 30.9 10 100 0.047 330 100 180 0.1 7.52 74.67
12 5.5 5.0 1.0 480 27 47 59.0 10 2.94 52.3 10 100 0.047 330 100 120 0.1 10.61 80.95
12 6 5.0 0.5 1000 27 47 64.9 10 7.15 52.3 10 47.5 0.033 33 100 51 0.1 10.71 73.33
12 6 5.5 1.0 480 27 47 64.9 10 3.16 59.0 10 100 0.047 330 100 110 0.1 11.47 83.91
16 6 5.0 1.0 480 27 47 64.9 10 3.16 52.3 10 100 0.047 330 100 110 0.1 10.69 74.59
17 6 5.0 0.2 480 130 47 64.9 10 3.16 52.3 10 100 0.220 330 100 110 0.1 10.81 76.84
22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated