Datasheet

TPS54120
SBVS180C –JANUARY 2012–REVISED JUNE 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION
(1)
SPECIFIED JUNCTION
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR TEMPERATURE RANGE
TPS54120 QFN-24 RGY -40°C to +125°C
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating temperature range (unless otherwise noted).
VALUE
MIN MAX UNIT
VIN, PVIN –0.3 20 V
PH –1 20 V
PH (10ns transient) –3 –1 V
BOOT –0.3 27 V
BOOT – PH 0 7 V
Voltage
LDOIN, OUT –0.3 7
LDOEN –0.3 V
LDOIN
+ 0.3
(2)
V
EN, RT/CLK, PWRGD –0.3 6 V
VSENSE, COMP, SS –0.3 3 V
FB, NR –0.3 3.6 V
OUT Internally limited A
RT/CLK ±100 µA
PH Internally limited A
Current
PVIN Internally limited A
COMP ±200 µA
PWRGD (sinking) –0.1 5 mA
Operating junction, T
J
–40 +150 °C
Temperature
Storage, T
stg
–55 +150 °C
Human body model (HBM) 2 kV
Electrostatic discharge ratings
Charged device model (CDM) 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
(2) V
EN
absolute maximum rating is V
LDOIN
+ 0.3 V or +7.0 V, whichever is smaller.
THERMAL INFORMATION
TPS54120
THERMAL METRIC
(1)
RGY (QFN) UNITS
24 PINS
θ
JA
Junction-to-ambient thermal resistance 45.1
θ
JC(top)
Junction-to-case(top) thermal resistance 48.2
θ
JB
Junction-to-board thermal resistance 22.0
°C/W
ψ
JT
Junction-to-top characterization parameter 2.1
ψ
JB
Junction-to-board characterization parameter 21.9
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance 8.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated