Datasheet

TPS54120
www.ti.com
SBVS180C JANUARY 2012REVISED JUNE 2012
START-UP TIME
SOFT-START OF THE SWITCHER
The rate at which the output voltage of the switcher rises up to the full operational level during the start-up phase
is controlled through the SS pin. A capacitor, C
SS
, is connected between the SS pin and the IC ground. The size
of the capacitor determines the soft-start ramp-up time (t
ss
, 10% to 90%), as shown in Equation 5:
t
SS
(ms) = C
(SS)
(nF) V
ref
(V)) / I
SS
(µA) (5)
The device has an internal pull-up current source of 2.3 µA = I
ss
that charges the external soft-start capacitor,
C
SS
. The voltage reference, V
ref
, for this device is 0.8 V. Thus, by sourcing a constant current onto the capacitor,
the device linearly ramps up the voltage on the SS pin, which corresponds to the voltage on the FB pin and thus,
the output voltage of the switcher.
If the input UVLO is triggered, the EN pin is pulled below 1.21 V, or a thermal shutdown event occurs, then the
device stops switching and enters low-current operation. At the subsequent power-up, when the shutdown
condition is removed, the device does not start switching until it has discharged the SS/TR pin to ground,
ensuring proper soft-start behavior.
NR SOFT-START TIME AND LDO START-UP
The NR capacitors main purpose is to filter the noise from the LDO bandgap, and thereby reduce the LDO output
noise. However, these capacitors also affect the start-up time of the LDO. The TPS54120 has a quick-start circuit
to quickly charge C
(NR)
, if it is present; see the Functional Block Diagram. At start-up, this quick-start switch is
closed, creating only 33 k of resistance between the band gap reference and the NR pin. The quick-start switch
opens approximately 2 ms after any device enabling event, and the resistance between the band gap reference
and the NR pin becomes higher in value (approximately 250 k) to form a very good low-pass (RC) filter. This
low-pass filter achieves very good noise reduction for the reference voltage.
Inrush current can be a problem in many applications. The 33-k resistance during the start-up period is
intentionally added to slow down the reference voltage ramp up, thus reducing the inrush current. For example,
the capacitance of connecting the recommended C
(NR)
value of 0.01 μF along with the 33-k resistance causes
an approximately 1-ms RC delay. Start-up time for the LDO with other C
(NR)
values can be determined by using
Figure 13 or calculated as shown in Equation 6:
t
STR
(s) = 76000 × C
(NR)
(F) (6)
Although the noise reduction effect is nearly saturated at 0.01 μF, connecting a C
(NR)
value greater than 0.01 μF
can help reduce noise slightly more; however, start-up time may become longer because the quick-start switch
opens after approximately 2 ms. That is, if CNR is not fully charged during this 2-ms period, C
(NR)
finishes
charging through a higher resistance of 250 kΩ, and takes much longer to fully charge. Note that a low leakage
C
(NR)
should be used; most ceramic capacitors are suitable.
POWER GOOD (PWRGD)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal
voltage reference, the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to place a 10-
k to 100-k pull-up resistor to a voltage source that is less than or equal to 5.5 V. The PWRGD is in a defined
state after the VIN input voltage is greater than 1 V, but with reduced current-sinking capability. The PWRGD pin
achieves full current-sinking capability after the VIN input voltage is greater than 4.5 V.
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal
reference voltage. The PWRGD is also pulled low if the input UVLO or thermal shutdown are asserted, the EN
pin is pulled low, or the SS/TR pin is less than 1.2 V, typically.
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