Datasheet

f (kHz)

R ( )

kΩ

100

150

200

250

200 300 400 500 600 700 800 900 1000 1100 1200

TPS54120

SBVS180C –JANUARY 2012–REVISED JUNE 2012

www.ti.com

ADJUSTABLE SWITCHING FREQUENCY AND SYNCHRONIZATION (RT/CLK)

The RT/CLK pin can be used to set the switching frequency of the device in two modes: RT and CLK.

RT MODE

A resistor, R

(RT)

, is connected between the RT/CLK pin and GND. The switching frequency of the device is

adjustable from 200 kHz to 1200 kHz by using a maximum of 240 kΩ and minimum of 40.2 kΩ, respectively. To

determine the value of the RT resistor for a given switching frequency (f

), use Equation 4 or the curve in

Figure 1:

(kΩ) = 60281 f

–1.033

(kHz) (4)

Figure 29. RT Set Resistor vs Switching Frequency

CLK MODE

In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the

external clock frequency with a phase-locked loop (PLL). CLK mode overrides RT mode. The device is able to

automatically detect the required mode and switch from RT mode to CLK mode. An internal PLL has been

implemented to allow synchronization between 200 kHz and 1.2 MHz, and to easily switch from RT mode to CLK

mode. To implement the synchronization feature, connect a square-wave clock signal to the RT/CLK pin with a

duty cycle between 20% to 80%. The clock signal amplitude must transition less than 0.8 V and greater than 2.0

V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both

RT mode and CLK mode are required, the device can be configured to have both RT resistor and external clock

connected at the same time to RT/CLK pin. Before the external clock is present, the device works in RT mode

and the switching frequency is set by RT resistor. When the external clock is present, CLK mode overrides RT

mode and ignores the RT resistor. The first time the SYNC pin is pulled above the RT/CLK high threshold (2.0

V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL

starts to lock on to the frequency of the external clock. It is not recommended to switch from the CLK mode back

to the RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching

frequency set by RT resistor.