Datasheet

TPS54120

SBVS180C –JANUARY 2012–REVISED JUNE 2012

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BOOTSTRAP VOLTAGE AND LOW DROPOUT OPERATION

The TPS54120 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and

PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the

BOOT pin voltage is less than VIN and the (BOOT – PH) voltage is below regulation. The value of this ceramic

capacitor should be 0.1 μF. A ceramic capacitor with an X7R- or X5R-grade dielectric with a voltage rating of 10

V or higher is recommended because of the stable characteristics over temperature and voltage.

To improve dropout, the device is designed to operate at 100% duty cycle, as long as the BOOT to PH pin

voltage is greater than the (BOOT – PH) UVLO threshold (typically 2.1 V). When the voltage between BOOT and

PH drops below the (BOOT – PH) UVLO threshold, the high-side MOSFET is turned off and the low-side

MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails,

100% duty-cycle operation can be achieved as long as (VIN – PVIN) > 4V and (V

(BOOT)

– V

(PH)

) > 2.1V; the

UVLO threshold for the BOOT pin.

NOTE

A boot resistor in series with the boot capacitor should never be used on the TPS54120.

OUTPUT OVERVOLTAGE PROTECTION (OVP)

The TPS54120 has an overvoltage protection (OVP) circuit on the switcher output to minimize overshoots on the

switcher output. This also protects the input of the LDO from experiencing overshoot above its rated values.

CAUTION

Any voltage above the absolute maximum rated input voltage into the LDOIN pin can

damage the device.

When the power-supply output is overloaded, the error amplifier compares the actual output voltage to the

internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a

considerable amount of time, the output of the error amplifier demands maximum output current. Once the

condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state

voltage. In some applications with small output capacitance, the dc-dc output voltage can respond faster than the

error amplifier. This leads to the possibility of a switcher output overshoot.

The OVP feature minimizes overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the

VSENSE pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off, preventing current

from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops below the OVP

threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.