Datasheet

TPS54120
www.ti.com SBVS180C –JANUARY 2012–REVISED JUNE 2012
ADJUSTING THE OUTPUT VOLTAGE
The output voltage of both the switcher and the LDO are adjustable. They are set with a resistor divider from the
output voltage to the feedback sensing pin. Use 1%-tolerance or better divider resistors for best accuracy.
The values of the LDO feedback resistors can be calculated using Equation 1:
V
(OUT)
= (R
4
+ R
5
) V
ref
/ R
5
Where:
V
ref
= 0.8 V
R4 = The resistor from the output to the FB pin of the LDO.
R5 = The resistor from the FB pin to ground of the LDO. (1)
The values of the switching regulator feedback resistors can be calculated using Equation 2:
DC-DC_OUT = (R
1
+ R
2
) V
ref
/ R
2
Where:
V
ref
= 0.8 V
R1 = The resistor from the switcher output at the inductor to the VSENSE pin of the switching regulator.
R2 = The resistor from the VSENSE pin to ground switching regulator. (2)
To improve efficiency at light loads, consider using larger-value resistors. Larger-value resistors may increase the
noise sensitivity at the VSENSE and FB pins and error from the VSENSE and FB pin input currents. Using a
value of 10 kΩ for R2 and R5 provides a good trade-off between these two issues.
POWER CONVERSION EFFICIENCY VERSUS OUTPUT NOISE
The configuration of the TPS54120 consists of a switching regulator followed by an LDO. The ability of the LDO
to reject the noise created by the switching regulator and not pass it to the LDO output is determined by the
power supply rejection (PSR) of the LDO. The PSR of an LDO depends on the LDO input to LDO output voltage
difference. The higher the voltage difference, the better the LDO ability to reject noise at its input. The LDO in the
TPS54120 has been designed to provide high, wide-bandwidth PSR with a minimum of input to output voltage
differential. At 1 A for the highest PSR performance, the input-to-output voltage differential should be set to 0.8 V
or greater.
The LDO voltage differential is also a primary contributor to the overall power loss in the TPS54120. The LDO
input and output voltage differentials contribution to the power loss is defined as the output current times the
input-to-output voltage differential, as shown in Equation 3:
Power Loss from the LDO = I
(OUT)
× (V
(LDOIN)
– V
(OUT)
) (3)
Therefore, for a 0.8-V drop at 1 A, this loss is 0.8 W. The impact of the power loss can be reduced by lowering
V
DO
; however, the PSR of the LDO may be impacted. In the Typical Characteristics section, Figure 6 and
Figure 7 show the trade-off between PSR and V
DO
for various output current levels and frequencies. For currents
less than 500mA, a V
DO
of 0.5 V does not have significant impact on PSR performance and provides a
substantial improvement to the power loss from the V
DO
.
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