Datasheet

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BOOT

VIN

PVIN

RT/CLK

COMP

GND

TPS54120

LDOIN

LDOEN VSENSE

OUT

ON/OFF

OUT

BOOT

DC-DC_OUT

R1 R2

(OUT)

TPS54120

www.ti.com

SBVS180C –JANUARY 2012–REVISED JUNE 2012

Low-Noise, 1-A Power Supply

with Integrated DC-DC Converter and Low-Dropout Regulator

FEATURES

DESCRIPTION

The TPS54120 combines the high-efficiency of a

• Low-Noise Output: 17 µV

RMS

at 100 Hz to

step-down switching (dc-dc) converter with a high

1 MHz

power-supply rejection (PSR), low-noise, low-dropout

• Wide Input Voltage Range: 4.5 V to 17 V

regulator (LDO) to provide an ultra low-noise power

• High Efficiency: 72% at 1 A, 12V Input

supply that delivers quiet power rails to noise-

sensitive applications.

• Excellent Load/Line Transient Response

With a wide input range of 4.5 V to 17 V, the

• Synchronizable to External Clock: 200 kHz to

TPS54120 is ideally suited for systems with 12-V

1.2 MHz

power busses, and supports a 1-A continuous output

• Small Package: 3.5 mm × 5.5 mm QFN-24

current. The output voltage can be set from 0.8 V to

6.0 V using external resistors. The dc-dc converter

APPLICATIONS

and LDO are completely configurable, allowing the

TPS54120 to be used in a wide range of low-noise

• Telecom Infrastructure

applications. In addition, the TPS54120 includes

• Pico and Femto Base Stations

features such as softstart, switching frequency

• Powering Sensitive Clocking Distribution

synchronization, and a power-good signal.

Circuits

The device is available in a space-saving, 3.5-mm ×

• Test and Measurement

5.5-mm QFN package, and is specified to operate

• Powering RF Components: VCOs, Receivers,

over a –40°C to +125°C junction temperature range.

ADCs

• Professional Audio

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 Low-Noise, 1-A Power Supply with Integrated DC-DC Converter and Low-Dropout Regulator FEATURES DESCRIPTION • The TPS54120 combines the high-efficiency of a step-down switching (dc-dc) converter with a high power-supply rejection (PSR), low-noise, low-dropout regulator (LDO) to provide an ultra low-noise power supply that delivers quiet power rails to noisesensitive applications.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS At TJ = –40°C to +125°C, V(PVIN) = V(VIN) = 12 V, V(LDOIN) = DC-DC_OUT (1) = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, C(OUT) = 100 μF, unless otherwise noted. TPS54120 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY (VIN AND PVIN PINS) V(PVIN) V(VIN) PVIN pin input voltage range 1.6 17 V VIN pin input voltage range 4.5 17 V UVLO threshold VIN rising 4.0 UVLO hysteresis 4.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, V(PVIN) = V(VIN) = 12 V, V(LDOIN) = DC-DC_OUT(1) = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, C(OUT) = 100 μF, unless otherwise noted. TPS54120 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LDO V(LDOIN) LDO input voltage range V(FB) FB pin voltage V(OUT) OUT pin voltage range 2.2 V(FB) OUT pin voltage accuracy I(OUT) ≤ 1 A, V(OUT_nom) + 0.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 PIN CONFIGURATION RGY PACKAGE QFN-24 (TOP VIEW) OUT LDOIN 1 24 OUT 2 23 LDOIN FB 3 22 NR GND 4 21 LDOEN NC 5 20 NC RT/CLK 6 19 PWRGD PGND 7 18 BOOT PGND 8 17 PH PVIN 9 16 PH PVIN 10 15 EN VIN 11 14 SS Thermal Pad 12 13 VSENSE COMP PIN DESCRIPTIONS PIN NAME NO. DESCRIPTION BOOT 18 A bootstrap capacitor is required between the BOOT and PH pins.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS At V(PVIN) = V(VIN)= 12 V, V(LDOIN) = DC-DC_OUT = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, COUT = 100 μF, and CSS = CNR = 0.01µF (see Figure 28), unless otherwise noted. LOAD REGULATION LOAD REGULATION UNDER LIGHT LOADS 3.399 3.399 + 125°C + 85°C + 25°C 0°C − 40°C 3.366 3.333 VOUT (V) VOUT (V) 3.333 + 125°C + 85°C + 25°C 0°C − 40°C 3.366 3.3 3.267 3.3 3.267 3.234 3.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At V(PVIN) = V(VIN)= 12 V, V(LDOIN) = DC-DC_OUT = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, COUT = 100 μF, and CSS = CNR = 0.01µF (see Figure 28), unless otherwise noted. POWER-SUPPLY RIPPLE REJECTION vs LDO DROPOUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 100 100 90 90 IOUT = 1 A 80 80 70 PSRR (dB) PSRR (dB) 70 60 50 40 30 10 0 0 0.5 1 1.5 2 VDO (V) 2.5 3 0 3.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At V(PVIN) = V(VIN)= 12 V, V(LDOIN) = DC-DC_OUT = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, COUT = 100 μF, and CSS = CNR = 0.01µF (see Figure 28), unless otherwise noted. START-UP TIME vs LDO NOISE-REDUCTION CAPACITANCE LINE TRANSIENT RESPONSE 19 18 RLOAD = 33 Ω CSS = 0.01 µF 0.02 VOUT Deviation VIN= 7 V to 12 V to 7 V (1 V/µs) 10 12 −0.04 10 −0.06 8 −0.08 6 1 −0.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At V(PVIN) = V(VIN)= 12 V, V(LDOIN) = DC-DC_OUT = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, COUT = 100 μF, and CSS = CNR = 0.01µF (see Figure 28), unless otherwise noted. EN PIN PULL-UP CURRENT vs TEMPERATURE 3.5 1.25 3.45 1.2 EN Pin Current (µA) EN Hysteresis Current (µA) EN PIN HYSTERESIS CURRENT vs TEMPERATURE 3.4 3.35 3.3 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 1.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At V(PVIN) = V(VIN)= 12 V, V(LDOIN) = DC-DC_OUT = 4.1 V, V(OUT) = 3.3 V, I(OUT) = 10 mA, V(EN) = floating, COUT = 100 μF, and CSS = CNR = 0.01µF (see Figure 28), unless otherwise noted.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com DETAILED DESCRIPTION TYPICAL APPLICATION Figure 28 shows a typical application diagram for the TPS54120. DC-DC_OUT R1 41.2 kW L1 22 mH CDC-DC_OUT 47 mF CBOOT 0.1 mF VIN 12 V R2 10 kW BOOT PH LDOIN LDOEN VSENSE R4 30.9 kW PVIN ON/OFF EN TPS54120 FB RT/CLK RRT 100 kW V(OUT) OUT VIN CFF 0.1 mF COUT 3.3 V 10 mF R5 10 kW SS CSS 0.01 mF COMP NR GND C2 330 pF R3 2.2 kW CNR 0.1 mF C1 0.047 mF Figure 28.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 ADJUSTING THE OUTPUT VOLTAGE The output voltage of both the switcher and the LDO are adjustable. They are set with a resistor divider from the output voltage to the feedback sensing pin. Use 1%-tolerance or better divider resistors for best accuracy. The values of the LDO feedback resistors can be calculated using Equation 1: V(OUT) = (R4 + R5) Vref / R5 Where: Vref = 0.8 V R4 = The resistor from the output to the FB pin of the LDO.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com BOOTSTRAP VOLTAGE AND LOW DROPOUT OPERATION The TPS54120 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and the (BOOT – PH) voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 OVERCURRENT PROTECTION SWITCHER OVERCURRENT PROTECTION The integrated switcher of the TPS54120 is protected from overcurrent conditions by using cycle-by-cycle current limiting on both MOSFETs, the low-side and the high-side. HIGH-SIDE MOSFET OVERCURRENT PROTECTION High-side MOSFET overcurrent protection is achieved by an internal current comparator that monitors the current in the high-side MOSFET on a cycle-by-cycle basis.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com ADJUSTABLE SWITCHING FREQUENCY AND SYNCHRONIZATION (RT/CLK) The RT/CLK pin can be used to set the switching frequency of the device in two modes: RT and CLK. RT MODE A resistor, R(RT), is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1200 kHz by using a maximum of 240 kΩ and minimum of 40.2 kΩ, respectively.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 START-UP TIME SOFT-START OF THE SWITCHER The rate at which the output voltage of the switcher rises up to the full operational level during the start-up phase is controlled through the SS pin. A capacitor, CSS, is connected between the SS pin and the IC ground.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com DEVICE ENABLE AND UNDERVOLTAGE LOCKOUT ADJUSTMENT SWITCHER ENABLE AND UNDERVOLTAGE LOCKOUT The EN pin is used to turn the switcher on and off. When the EN pin voltage exceeds the threshold voltage, the device begins operating. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low IQ state. The EN pin has an internal pull-up current source; float or drive the EN pin to enable the device.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 The EN pin has a small pull-up current (Ip) that sets the state of the pin to enable (default) when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function because it increases by Ih when the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 7 and Equation 8.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com SMALL-SIGNAL MODEL FOR LOOP RESPONSE Figure 33 shows an equivalent model for the device control loop. This model can be run in a circuit simulation program to check frequency and transient responses. The error amplifier is a transconductance amplifier with a gM of 1300 mA/V, and can be modeled using an ideal voltage-controlled current source. Resistor Roea (2.38 MΩ) and capacitor Coea (20.
PAGE 21
TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 APPLICATION INFORMATION DESIGN METHODOLOGY The TPS54120 has a low-noise output voltage range from 0.8 V to 6.0 V with an output current of up to 1 A. To simplify design efforts using the TPS54120, typical designs for common applications are listed in Table 1 according to the typical schematic diagram shown in Figure 34.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com The internal LDO of the TPS54120 is designed to be stable with standard ceramic output capacitors with values of 4.7 μF or larger; higher values are recommended for better noise performance. A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating.
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TPS54120 www.ti.com SBVS180C – JANUARY 2012 – REVISED JUNE 2012 PCB LAYOUT GUIDELINES PACKAGE MOUNTING Solder pad footprint recommendations for the TPS54120 are available at the end of this product datasheet and at www.ti.com. BOARD LAYOUT RECOMMENDATIONS FOR HIGH-PSR AND LOW-NOISE PERFORMANCE Correct printed circuit board (PCB) layout is a critical portion of good power-supply design and is a particularly important for the high PSR and low-noise performance of the TPS54120.
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TPS54120 SBVS180C – JANUARY 2012 – REVISED JUNE 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2012) to Revision C Page • Added capacitor to Figure 28 .............................................................................................................................................. 12 • Changed Equation 3 ...........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54120RGYR VQFN RGY 24 3000 330.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1 TPS54120RGYT VQFN RGY 24 250 180.0 12.4 3.8 5.8 1.2 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54120RGYR VQFN RGY 24 3000 367.0 367.0 35.0 TPS54120RGYT VQFN RGY 24 250 210.0 185.0 35.
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