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Board Layout

Figure 8. TPS54120 Thermal Image

5 Board Layout

This section provides a description of the TPS54120, board layout, and layer illustrations.

5.1 Layout Description

The board layout for the TPS54120 evaluation board is shown in Figure 9 through Figure 12. The board

consists of 4 layers. It is laid out in such a way the analog ground of the LDO is shielded as much as

possible from the noise of the switcher. Also, critical analog circuits such as the voltage set point divider,

frequency set resistor, slow start capacitor and compensation components are terminated to ground using

a via separate from the power ground pour. The topside layer of the EVM is laid out in a manner typical of

a user application.

The top layer contains the analog ground of the LDO and a portion of the output power ground of the SW

side. The first internal layer is connected to the power pad and the analog ground of the IC; mostly this

layer is used for power dissipation. Only a few traces are implemented on this layer such as the LDO

enable, and the PWRGD test point trace.

The second internal layer is mostly used for analog ground as well. For shielding the LDO ground from the

switch node noise, a small isolated power ground plane is made in the center of this layer to reduce

capacitive coupling with analog ground. This layer also contains the input voltage trace of the switcher

connecting the input cap and the connector J3.

About one quarter of the bottom layer contains the main input power ground trace. In the center of the

layer, the inductor (L1) and the output caps (C9, C10) of the switcher are located. The remaining surface

area is connected to the analog ground of the top and the internal layers through vias. Some of these vias

are directly under the TPS54120 device to provide a thermal path from the top-side ground plane to the

internal and bottom-side ground plane.

SLVU641– January 2012 TPS54120EVM, Low Noise 1A Power Supply Evaluation Module

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