Datasheet
TPS54110−Q1
SLVS837 − JULY 2008
www.ti.com
2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
J
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
−40°C to 125°C HTSSOP − PW Reel of 2000 TPS54110QPWPRQ1 54110Q
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at http://www.ti.com.
(2))
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
VIN, SS/ENA, SYNC −0.3 V to 7 V
Itlt V
RT −0.3 V to 6 V
Input voltage range, V
I
VSENSE −0.3 V to 4 V
BOOT −0.3 V to 17 V
Ot t lt V
VBIAS, PWRGD, COMP −0.3 V to 7 V
Output voltage range, V
O
PH −0.6 V to 10 V
StI
PH Internally Limited
Source current, I
O
COMP, VBIAS 6 mA
PH 3.5 A
Sink current
COMP 6 mA
Sink
current
SS/ENA,PWRGD 10 mA
Voltage differential AGND to PGND ±0.3 V
Continuous power dissipation
See Dissipation
Ratings Table
Operating virtual junction temperature range, T
J
−40°C to 150°C
Storage temperature, T
stg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage range, V
I
3 6 V
Operating junction temperature, T
J
−40 125 °C
DISSIPATION RATINGS
(1)
(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T
A
= 25°C
POWER RATING
T
A
= 70°C
POWER RATING
T
A
= 85°C
POWER RATING
20-pin PWP with solder 26.0°C/W 3.85 W
(3)
2.12 W 1.54 W
20-pin PWP without solder 57.5°C/W 1.73 W 0.96 W 0.69 W
(1)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2)
Test board conditions:
1. 3-in × 3-in, two layers, Thickness: 0.062 in
2. 1.5-oz copper traces located on the top of the PCB
3. 1.5-oz copper ground plane on the bottom of the PCB
4. Ten thermal vias (see recommended land pattern in application section of this data sheet)
(3)
Maximum power dissipation may be limited by overcurrent protection.