Datasheet

TPS54110−Q1
SLVS837 − JULY 2008
www.ti.com
19
PCB LAYOUT CONSIDERATIONS
The VIN pins are connected together on the printed board
(PCB) and bypassed with a low-ESR ceramic bypass
capacitor. Minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the TPS54110
ground pins. The recommended bypass capacitor is 10-µF
(minimum) ceramic with X5R or X7R dielectric. The
optimum placement is closest to the VIN pins and the
AGND and PGND pins. See Figure 31 for a layout
example. It has an area of ground on the top layer directly
under the IC, with an exposed area for connection to the
PowerPAD. Use vias to connect this ground area to any
internal ground planes. Use additional vias at the ground
side of the input and output filter capacitors as well. Tie the
AGND and PGND pins to the PCB ground area under the
device as shown. Use a separate wide trace for the
analog-ground path, connecting the voltage set-point
divider, timing resistor RT, slow-start capacitor, and
bias-capacitor grounds. Tie the PH pins together and route
to the output inductor. Since the PH connection is the
switching node, locate the inductor very close to the PH
pins, and minimize the area of the conductor to prevent
excessive capacitive coupling. Connect the boot capacitor
between the phase node and the BOOT pin as shown.
Keep the boot capacitor close to the IC and minimize the
conductor trace lengths. Connect the output-filter
capacitor(s) as shown between the VOUT trace and
PGND. It is important to keep the loop formed by the PH
pins, Lout, Cout, and PGND as small as is practical. Place
the compensation components from the VOUT trace to the
VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin-out, they must be
somewhat closely routed while maintaining as much
separation as possible, yet keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace as well.
AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
PH
PH
PH
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
VOUT
PH
VIN
TOPSIDE GROUND AREA
VIA to Ground Plane
ANALOG GROUND TRACE
Exposed
Powerpad
Area
COMPENSATION
NETWORK
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
FREQUENCY SET RESISTOR
SLOW START
CAPACITOR
BIAS CAPACITOR
PGND
COUT
LOUT
Figure 31. PC Board Layout Example