Datasheet

TPS54110−Q1
SLVS837 − JULY 2008
www.ti.com
12
GROUNDING AND PowerPAD LAYOUT
The TPS54110 has two internal grounds (analog and
power). Inside the TPS54110, the analog ground connects
all noise-sensitive signals, while the power ground
connects the noisier power signals. The PowerPAD must
be tied directly to AGND. Noise injected between the two
grounds can degrade the performance of the TPS54110,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground planes are
recommended. Tie these two planes together directly at
the IC to reduce noise between the two grounds. The only
components that tie directly to the power-ground plane are
the input capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54110. The layout of the TPS54110 evaluation
module represents recommended layout for a 2-layer
board. Documentation for the TPS54110 evaluation
module is obtained from the Texas Instruments web site
under the TPS54110 product folder and in the application
note, TI literature number SLVA109.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipation area. A
3-inch-by-3-inch plane of 1-ounce copper is
recommended, though not mandatory, depending on
ambient temperature and airflow. Most applications have
larger areas of internal ground plane available. Connect
the PowerPAD to the largest area available. Additional
areas on the top or bottom layers also help dissipate heat.
Use any area available when 1.5-A or greater operation is
desired. Connect the exposed area of the PowerPAD to
the analog ground-plane layer with 0.013-inch-diameter
vias to avoid solder wicking through the vias. An adequate
design includes six vias in the PowerPAD area with four
additional vias located under the device package. The size
of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional
vias in areas not under the device package enhance
thermal performance.
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
0.2454
0.0150
0.06
0.0256
0.1700
0.1340
0.0620
0.0400
0.0400
0.0400
0.0600
0.0227
0.0600
0.1010
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
0.2560
Figure 10. Recommended Land Pattern for 20-Pin PWP PowerPAD