Datasheet

6
4
5
C3
0.047 Fµ
19
20
V
I
5 V
+
C1
470 Fµ
PWRGD_3P3
R7
10 kΩ
U1
TPS54110PWP
R4
71.5 kΩ
C4
0.1 Fµ
C9
10 Fµ
21
11
12
13
14
15
16
17
18
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PWPD
R3
1.74 kΩ
C6
1000 pF
C7
47 pF
10
9
8
7
6
5
4
3
2
1
C8
560 pF
R5
432 Ω
R1
10 kΩ
R2
3.74 kΩ
L1
1 Hµ
1 2
3.3 V at 1.5 A
C14
0.047 Fµ
19
20
PWRGD_1P5
R8
10 kΩ
U2
TPS54110PWP
R9
71.5 kΩ
C10
0.1 Fµ
C15
10 Fµ
21
11
12
13
14
15
16
17
18
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PWPD
R6
1.74 kΩ
C5
1000 pF
C11
47 pF
10
9
8
7
3
2
1
C13
560 pF
R12
432 Ω
R11
10 kΩ
R10
14.7 kΩ
L2
1 Hµ
1 2
1.5 V at 1.5 A
C2
10 Fµ
C12
10 Fµ
V
OUT1
V
OUT2
TPS54110
www.ti.com SLVS500C –DECEMBER 2003– REVISED FEBRUARY 2011
Two-Output Sequenced-Startup Application
Figure 29. TPS54110 Sequencing Application Circuit
In Figure 29, the power-good output of U1 is used as a sequencing signal in a two-output design. Connecting the
PWRGD pin of U1 to the SS/ENA pin of U2 causes the 1.5-V output to ramp up after the 3.3-V output is within
regulation. Figure 30 shows the startup waveforms associated with this circuit.
When V
IN
reaches the UVLO-start threshold, the U1 output ramps up towards the 3.3-V set point. After the output
reaches 90 percent of 3.3 V, the U1 asserts the power-good signal driving the U2 SS/ENA input high. The output
of U2 then ramps up towards the final output set point of 1.5 V.
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