Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 20

(6,3 mm x 6,4 mm)

Typical Size

VIN

TPS54110

BOOT

PGND

COMP

VSENSE

AGND

VBIAS

Compensation

Network

Input Output

100

0 0.25 0 .5 0 .75 1 1.25 1. 5

I -

Output Current - A

Efficiency - %

EFFICIENCY

OUTPUT CURRENT

100 µF

2200 pF

0.047 µF

0.1 µF

10 µF

3.92 kΩ

2.05 kΩ

3.92 kΩ

19.1 kΩ

6.8µH

2700 pF

33 pF

Simplified Schematic

TPS54110

www.ti.com

SLVS500C –DECEMBER 2003– REVISED FEBRUARY 2011

3-V TO 6-V Input, 1.5-A Output Synchronous-Buck PWM

Switcher with Integrated FETs ( SWIFT™)

Check for Samples: TPS54110

FEATURES

DESCRIPTION

• Integrated MOSFET Switches for High

As members of the SWIFT family of dc/dc regulators,

Efficiency at 1.5-A Continuous Output Source

the TPS54110 low-input-voltage high-output-current

or Sink Current

synchronous-buck PWM converter integrates all

required active components. Included on the

• 0.9-V to 3.3-V Adjustable Output Voltage With

substrate with the listed features are a true, high-

1% Accuracy

performance, voltage error amplifier that provides

• Externally Compensated for Design Flexibility

high performance under transient conditions; an

• Fast Transient Response

undervoltage-lockout circuit to prevent start-up until

the input voltage reaches 3 V; an internally and

• Wide PWM Frequency: Fixed 350 kHz, 550 kHz,

externally set slow-start circuit to limit in-rush

or Adjustable 280 kHz to 700 kHz

currents; and a power-good output useful for

• Load Protected by Peak Current Limit and

processor/logic reset, fault signaling, and supply

Thermal Shutdown

sequencing.

• Integrated Solution Reduces Board Area and

The TPS54110 device is available in a thermally

Total Cost

enhanced 20-pin TSSOP (PWP) PowerPAD™

package, which eliminates bulky heatsinks. TI

APPLICATIONS

provides evaluation modules and the SWIFT designer

software tool to aid in quickly achieving high-

• Low-Voltage, High-Density Systems With

performance power supply designs to meet

Power Distributed at 5 V or 3.3 V

aggressive equipment development cycles.

• Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

• Broadband, Networking, and Optical

Communications Infrastructure

• Portable Computing/Notebook PCs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
Typical Size (6,3 mm x 6,4 mm) TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com 3-V TO 6-V Input, 1.5-A Output Synchronous-Buck PWM Switcher with Integrated FETs ( SWIFT™) Check for Samples: TPS54110 FEATURES DESCRIPTION • As members of the SWIFT family of dc/dc regulators, the TPS54110 low-input-voltage high-output-current synchronous-buck PWM converter integrates all required active components.
PAGE 2
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ OUTPUT VOLTAGE PACKAGED DEVICES PLASTIC HTSSOP (PWP) (1) –40°C to 125°C Adjustable to 0.891 V TPS54110PWP The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e.
PAGE 3
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX fs = 350 kHz, SYNC ≤ 0.8 V, RT open 4.5 8.5 fs = 550 kHz, Phase pin open, SYNC ≥ 2.5 V, RT open, 5.8 9.6 1 1.4 2.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.
PAGE 5
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT SYNC SS/ENA VBIAS VIN VIN VIN PGND PGND PGND TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. AGND 1 Analog ground—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD. BOOT 5 Bootstrap input. 0.022-µF to 0.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V REG VBIAS SHUTDOWN VIN ILIM Comparator Thermal Shutdown 150C ° 3- 6V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE IO = 1.5 A 0.5 0.4 0.3 0.2 0.1 VI = 5 V IO = 1.5 A 0.3 0.2 0.1 0 −40 0 −40 0 25 85 f − Internally Set Oscillator Frequency −kHz 0.4 VI = 3.3 V Drain-Source On-State Resistance − Ω Drain-Source On-State Resistance − Ω 0.6 125 0 25 125 85 750 650 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54110 application. The TPS54110 can provide up to 1.5 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed PowerPAD underneath the device must be soldered down to the printed-circuit board. R7 10 kΩ VIN (4.5 − 5.5 V) C8 2200 pF PWRGD + C1 10 µF U2 TPS54110PWP R4 71.5 kΩ 20 19 18 17 16 15 14 C5 .
PAGE 9
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com Alternately, the TPS54110 can be set to preprogrammed switching frequencies of 350 kHz or 550 kHz by connecting pins RT and SYNC as shown in Table 2. Table 2. Design Parameters FREQUENCY RT SYNC 350 kHz Float Float or AGND 550 kHz Float ≥ 2.5 V Input Capacitors The TPS54110 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 2 IL(RMS) = I OUT(MAX) + 1 æ VOUT ´ (VIN(MAX) - VOUT ) ö ´ç ÷ 12 è VIN(MAX) ´ LOUT ´ FSW ´ 0.8 ø www.ti.com 2 (5) The peak inductor current is determined from Equation 6: VOUT ´ (VIN(MAX)-VOUT) IL(PK) = IOUT(MAX) + 1.6 ´ VIN(MAX) ´ LOUT ´ FSW (6) For this design, the RMS inductor current is 1.503 A and the peak inductor current is 1.673 A. The inductor chosen is a Coilcraft DS3316P-682 6.8 µH. It has a saturationcurrent rating of 2.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com There are a number of different ways to design a compensation network. This procedure outlines a relatively simple procedure that produces good results with most output filter combinations. Use the SWIFT Designer Software for designs with unusually high closed-loop crossover frequencies; with low-value, low-ESR output capacitors such as ceramics; or if you are unsure about the design procedure.
PAGE 12
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com The first zero, fZ1 is located at one half the output filter LC corner frequency, so R3 is calculated from: 1 R3 = pC6¦LC (19) The second zero, fZ2 is located at the output filter LC corner frequency, so C8 is calculated from: 1 C8 = 2pR1¦LC (20) The first pole, fP1 is located to coincide with output filter ESR zero frequency.
PAGE 13
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com 6 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance Minimum Recommended Thermal Vias: 6 × .013 dia. Inside Powerpad Area 4 × .018 dia. Under Device as Shown. Additional .018 dia. Vias May be Used if Top Side Analog Ground Area is Extended. 0.0150 0.06 0.0227 0.0600 0.0400 0.2560 0.2454 0.1010 0.0400 0.0600 0.0256 0.1700 0.1340 0.0620 0.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com PERFORMANCE GRAPHS All performance data shown for VI = 5 V, VO = 3.3 V, fs = 700 kHz, TA = 25°C, Figure 9 EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT 1.2 100 0.05 95 Efficiency − % 85 80 75 70 65 60 1 Output Voltage Varistion − % PD − Power Dissipation − W 0.04 90 0.8 0.6 0.4 0.2 0.03 0.02 0.01 0 −0.01 −0.02 −0.03 −0.04 55 50 0 0.25 0.5 0.75 1 1.25 1.
PAGE 15
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com Very-Small Form-Factor Application R7 10 kΩ VIN C8 560 pF PWRGD + R4 71.5 kΩ C1 OPEN U2 TPS54110PWP 20 19 18 17 16 15 14 C5 OPEN C4 0.1 µF C9 10 µF 13 12 11 RT AGND SYNC SS/ENA VSENSE COMP VBIAS PWRGD VIN BOOT VIN PH VIN PH PGND PH PGND PH 1 R3 1.74 kΩ C6 1000 pF 2 3 4 5 R5 432 Ω R1 10.0 kΩ R2 14.7 kΩ C7 47 pF C3 0.047 µF 6 7 8 L1 1 µH 9 10 PGND PH PwrPd 1 2 1.5 V at 1.5 A C2 10 µF 21 Figure 20.
PAGE 16
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com All performance data shown for VI = 5 V, VO = 1.5 V, FS = 700 kHz, TA = 25°C, Figure 20 EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT 100 0.1 95 Efficiency − % 85 VI = 5 V 80 75 70 65 1.2 Output Voltage Varistion − % PD − Power Dissipation − W 0.08 90 1 0.8 0.6 VI = 5 V 0.4 VI = 3.3 V 60 55 0.2 VI = 3.3 V 0.06 0.04 0.02 −0.04 0 0.25 0.5 0.75 1 1.25 −0.
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TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com Two-Output Sequenced-Startup Application PWRGD_3P3 VI 5 V R7 C8 560 pF 10 kΩ + R4 71.5 kΩ C1 470 µF U1 TPS54110PWP 20 RT AGND 19 SYNC VSENSE 18 SS/ENA COMP 17 VBIAS PWRGD 16 VIN BOOT 15 VIN PH 14 VIN PH 13 PGND PH 12 PH PGND 11 PGND PH PWPD 21 C4 0.1 µF C9 10 µF 1 2 3 4 5 6 C6 R3 1.74 kΩ 1000 pF R1 10 kΩ R2 3.74 kΩ C7 47 pF C3 0.047 µF 7 8 9 L1 1 µH 10 1 3.3 V at 1.
PAGE 18
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com VIN − 5 V/div U1 − VOUT1 3.3 − 2 V/div U1 PWRGD − 5 V/div U2 − VOUT2 1.5 − 2 V/div Figure 30.
PAGE 19
TPS54110 www.ti.com SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54110 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins.
PAGE 20
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 SWITCHING FREQUENCY= www.ti.com 100kW ´ 500 kHz R (27) External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets the free-running frequency to 80% of the synchronization signal. Table 3 summarizes the frequency selection configurations. Table 3.
PAGE 21
TPS54110 www.ti.com SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 Overcurrent Protection Cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current-limit threshold. A 100-ns leading-edge blanking circuit prevents false tripping of the current limit.
PAGE 22
TPS54110 SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011 www.ti.com ANALOG GROUND TRACE FREQUENCY SET RESISTOR AGND RT SYNC VSENSE COMPENSATION NETWORK COMP SS/ENA PWRGD BOOT CAPACITOR BOOT SLOW START CAPACITOR VBIAS Exposed Powerpad Area BIAS CAPACITOR VIN PH VIN PH VIN PH PGND PH PGND PH PGND VIN VOUT LOUT OUTPUT INDUCTOR PH COUT OUTPUT FILTER CAPACITOR INPUT BYPASS CAPACITOR INPUT BULK FILTER PGND TOPSIDE GROUND AREA VIA to Ground Plane Figure 31.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54110PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54110PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.