Datasheet

Layout
3-2
3.1 Layout
The board layout for the TPS54110EVM−044 is shown in Figure 3−1 through
Figure 3−3. The top side layer of the TPS54110EVM−044 is laid out in a
manner typical of a user application that is optimized for small size. A small
footprint Coilcraft DO3314−103MX inductor and 0805 10-µF ceramic
capacitor are used in the output filter. 0402 case size components are used
when possible to further reduce circuit area. The top and bottom layers are
1.5-oz. copper.
The top layer contains the main power traces for V
I
, V
O
, and V
(phase)
. Also, on
the top layer are connections for the remaining pins of the TPS54110 and a
large area filled with ground. The bottom layer contains ground and V
O
copper
areas, and some signal routing. The top and bottom ground traces are
connected with multiple vias placed around the board including 10 vias directly
under the TPS54110 device to provide a thermal path from the PowerPAD
land to ground.
The input decoupling capacitors (C5 and C9), bias-decoupling capacitor (C4),
and bootstrap capacitor (C3) are all located as close to the IC as possible. In
addition, the compensation components are also kept close to the IC. The
compensation circuit ties to the output voltage at the point of regulation,
adjacent to the high-frequency bypass output capacitor.
Figure 3−1. Top Side Layout