Datasheet

VSENSE
COMP
GND
PH
BOOT
VIN
EN
RT/CLK
Frequency Set
Resistor
Boot
Capacitor
Input
Capacitor
Output
Capacitor
VOUT
Output
Inductor
Compensation
Network
Feedback
Resistors
UVLO
Adjust
Resistor
VIN
GND
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Signal VIA
TPS54062
www.ti.com SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Figure 49. Input and Output Ripple in CCM
Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See
Figure 50 for a PCB layout example. Since the PH connection is the switching node and output inductor should
be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive
coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the
IC and routed with minimal lengths of trace. The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has
been shown to produce good results and is meant as a guideline.
Figure 50. PCB Layout Example
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