Datasheet

RT/CLK
TPS54062
Clock
Source
PLL
RT
RT/CLK
TPS54062
Hi-Z
Clock
Source
PLL
RT
OUTSC LS CL DC CL
SW
ON IN CL HS CL LS
V + R × I + R I
div
(shift) = ×
t V I R + I R
f
f
æ ö æ ö
´
ç ÷ ç ÷
- ´ ´
è ø è ø
OUT LS O DC O
SW
ON IN O HS O LS
V + R I + R I
1
(maxskip) =
t V I R + I R
f
æ ö æ ö
´ ´
´
ç ÷ ç ÷
- ´ ´
è ø è ø
TPS54062
www.ti.com SLVSAV1B –MAY 2011–REVISED AUGUST 2012
(5)
(6)
Where:
I
O
= Output current
I
CL
= Current Limit
V
IN
= Input Voltage
V
OUT
= Output Voltage
V
OUTSC
Output Voltage during short
R
DC
= Inductor resistance
R
HS
= High side MOSFET resistance
R
LS
= Low side MOSFET resistance
t
on
= Controllable on time
fdiv = Frequency divide (equals 1, 2, 4, or 8)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 19. The square wave amplitude must transition lower than 0.5 V and higher than 1.3V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40ns. The synchronization frequency range
is 300 kHz to 400 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 19 through another resistor (e.g.,
50Ω) to ground for clock signal that are not Hi-Z or 3-state during the off state. The sum of the resistance should
set the switching frequency close to the external CLK frequency. It is recommended to ac couple the
synchronization signal through a 10pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above
the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage
source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal.
Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with
the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds. When
the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions.
Figure 19. Synchronizing to a System Clock
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS54062