Datasheet

V 0.8 V
OUT
R = R
HS LS
0.8 V
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TPS54062
www.ti.com SLVSAV1B –MAY 2011–REVISED AUGUST 2012
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54062 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level.
Slope Compensation Output Current
The TPS54062 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations.
Error Amplifier
The TPS54062 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the internal slow start voltage or the internal 0.8 V voltage reference. The
transconductance (gm) of the error amplifier is 102 µA/V during normal operation. During the slow start
operation, the transconductance is a fraction of the normal operating gm. The frequency compensation
components (capacitor, series resistor and capacitor) are added to the COMP pin to ground.
Voltage Reference
The voltage reference system produces a precise ±2 voltage reference over temperature by scaling the output of
a temperature stable band-gap circuit
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10kΩ for the R
LS
resistor and use the Equation 1 to
calculate R
HS
.
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54062 is enabled when the VIN pin voltage rises above 4.53 V and the EN pin voltage exceeds the EN
rising threshold of 1.24 V. The EN pin has an internal pull-up current source, I1, of 1.2 µA that provides the
default enabled condition when the EN pin floats.
If an application requires a higher input undervoltage lockout (UVLO) threshold, use the circuit shown in
Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.24 V,
an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below
1.14 V, the 3.5 µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis.
Use Equation 2 to calculate R
UVLO1
for the desired input start and stop voltages . Use Equation 3 to similarly
calculate R
UVLO2
.
In applications designed to start at relatively low input voltages (e.g., from 4.7 V to 10V) and withstand high input
voltages (e.g., from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum
voltage of 8 V during the high input voltage condition. It is recommended to use a zener diode to clamp the pin
voltage below the absolute maximum rating.
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Product Folder Link(s): TPS54062