Datasheet
1
C1
C4
C5
C6
C7
C8
R1
R2
R3
R4
R5
R6
R7
J2
TP1
TP3
TP4
TP5
TP6
TP2
U1
JP1
L1
J1
C3
C2
TP7
Texas Instruments
PWR142 Rev. A
VOUT
GND
GND
VIN
GND
GND
GND
VOUT
VIN
PH
TPS54061EVM-142
EN GND
LOOP
C1
C4
C5
C6
C7
C8
R1
R2
R3
R4
R5
R6
R7
J2
TP1
TP3
TP4
TP5
TP6
TP2
U1
JP1
L1
J1
C3
C2
TP7
www.ti.com
Board Layout
3 Board Layout
This section provides a description of the TPS54061EVM-142, board layout, and layer illustrations.
3.1 Layout
The board layout for the TPS54061EVM-142 is shown in Figure 18 through Figure 20. The top-side layer
of the EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz
copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54061 and a large area filled with ground. The bottom layer
contains ground and a signal route for the BOOT capacitor. The top and bottom and internal ground traces
are connected with multiple vias placed around the board including four vias directly under the TPS54061
device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors (C2 and C3), bootstrap capacitor (C4), and frequency set resistor (R3)
are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components
are also kept close to the IC. The voltage divider network ties to the output voltage at the point of
regulation, the copper V
OUT
trace past the output connector (J2). For the TPS54061, an additional input
bulk capacitor may be required (C1), depending on the EVM connection to the input supply.
Figure 18. TPS54061EVM-142 Top Assembly and Silkscreen
13
SLVU721–May 2012 Evaluation Module for TPS54061 Synchronous Step-Down SWIFT
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated