Datasheet

O
IN
IN SW
I
0.25
C
V ripple f
æ ö
³ ´
ç ÷
è ø
( )
INmin OUT
OUT
IN OUT
INmin INmin
V V
V
IC rms I
V V
-
= ´ ´
TPS54061
SLVSBB7C –MAY 2012–REVISED JANUARY 2014 www.ti.com
because they have a high capacitance to volume ratio and are fairly stable over temperature. The effective value
of a capacitor decreases as the dc bias across a capacitor increases. For this example design, a ceramic
capacitor with at least a 60 V voltage rating is required to support the maximum input voltage. The input
capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated
by rearranging Equation 18.
Using the design example values, Ioutmax = 200 mA, C
IN
= 2.2 µF, ƒ
SW
= 400 kHz, yields an input voltage ripple
of 56.8 mV and an rms input ripple current of 98.5 mA.
(17)
(18)
Bootstrap Capacitor Selection
A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54061. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 7.50 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.50 V (UVLO stop). The programmable UVLO and enable
voltages are set by connecting resistor divider between Vin and ground to the EN pin. Equation 2 and Equation 3
can be used to calculate the resistance values necessary. For example, a 196 kΩ resistor between Vin and EN
and a 36.5 kΩ resistor between EN and ground are required to produce the 7.50 and 6.50 volt start and stop
voltages. See the Enable and Adjusting Undervoltage Lockout section for additional considerations in high input
voltage applications.
Output Voltage and Feedback Resistors Selection
For the example design, 10 kΩ was selected for R
LS
. Using Equation 1, R
HS
is calculated as 31.46 kΩ. The
nearest standard 1% resistor is 31.6 kΩ.
Closing the Loop
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 19 and
Equation 20. For Cout, use a derated value of 6.0 µF. Use Equation 21 and Equation 22, to estimate a starting
point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 1015 Hz and
fzero is 5584 kHz.
Equation 21 is the geometric mean of the modulator pole and the ESR zero and Equation 22 is the mean of
modulator pole and the switching frequency. Equation 21 yields 119.2 kHz and Equation 22 gives 17.9 kHz. Use
a frequency near the lower value of Equation 21 or Equation 22 for an initial crossover frequency.
For this example, fco of 17.9 kHz is used. Next, the compensation components are calculated. A resistor in
series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components
forms the compensating pole.
To determine the compensation resistor, R
COMP
, use Equation 23. Assume the power stage transconductance,
gmps, is 1.00 A/V. The output voltage, Vo, reference voltage, V
REF
, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 108 µA/V, respectively.
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