Datasheet

RIPPLE
C
RIPPLE
V
R
I
£
OUT
O
OUT
I
2
C 3
V sw
D
³ ´
D f
( )
2 2
OH OL
O O
2
2
OUT OUT OUT
I I
C 2 L
V + V V
-
³ ´
D -
RIPPLE
O
RIPPLE SW
I
1
C 1
V 8 f
æ ö
³ ´
ç ÷
´
è ø
( )
OUT IN OUT
O
IN O SW
V V max V
1
IC rms =
V max L
12
f
æ ö
´ -
´
ç ÷
ç ÷
´ ´
è ø
TPS54061
www.ti.com
SLVSBB7C MAY 2012REVISED JANUARY 2014
Using these values gives a minimum capacitance of 3.79 µF. This does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into
account.
The low side FET of the regulator emulates a diode so it can not sink current so any stored energy in the
inductor will produce an output voltage overshoot when the load current rapidly decreases, as in Figure 28. The
output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load
current to a lower load current. The excess energy that gets stored in the output capacitor will increase the
voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these
transient periods. Equation 14 is used to calculate the minimum capacitance input the output voltage overshoot
to a desired value, where
LO
is the value of the inductor, I
OH
is the output current under heavy load, I
OL
is the
output under light load, V
O
+ΔV
O
is the final peak output voltage, and Vi is the initial capacitor voltage. For this
example, the worst case load step will be from 150 mA to 50 mA. The output voltage will increase during this
load transition and must be limited to 4% of the output voltage to satisy the design goal. This will make V
O
+ΔV
O
= 1.04 × 3.3 = 3.432 V. V
O
is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using
these numbers in Equation 14 yields a minimum capacitance of 2.25 µF.
Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where f
SW
is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 13 yields 1.48 µF. Equation 16 calculates the maximum ESR an output
capacitor can have to meet the output voltage ripple specification. Equation 16 indicates the ESR should be less
than 0.160 Ω.
The most stringent criteria for the output capacitor is 3.79 µF of capacitance to maintain the output voltage
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias will increase this minimum value. For this
example, 10 µF, 10V X5R ceramic capacitor with 0.003 Ω of ESR in a 1206 package is used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.
Equation 12 can be used to calculate the RMS ripple current the output capacitor needs to support. For this
example, Equation 12 yields 10.23 mA.
(12)
(13)
(14)
(15)
(16)
Input capacitor
The TPS54061 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF of
effective capacitance. The effective capacitance includes any deration for dc bias effects. The voltage rating of
the input capacitor must be greater than the maximum input voltage. The capacitor must also have an rms
current rating greater than the maximum rms input current. The input rms current can be calculated using
Equation 17. The value of a ceramic capacitor varies significantly over temperature and the dc bias applied to the
capacitor. The capacitance variations with temperature can be minimized by selecting a dielectric material that is
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
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