Datasheet

OUTSC LS CL DC CL
SW
ON IN CL HS CL LS
V + R × I + R I
div
(shift) = ×
t V I R + I R
f
f
æ ö æ ö
´
ç ÷ ç ÷
- ´ ´
è ø è ø
OUT LS O DC O
SW
ON IN O HS O LS
V + R I + R I
1
(maxskip) =
t V I R + I R
f
æ ö æ ö
´ ´
´
ç ÷ ç ÷
- ´ ´
è ø è ø
TPS54061
www.ti.com SLVSBB7C –MAY 2012–REVISED JANUARY 2014
To enable higher switching frequency at high input voltages, the TPS54061 implements a frequency shift. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum input
voltage limit in which the device operates and still have frequency shift protection. During short-circuit events
(particularly with high input voltage applications), the control loop has a finite minimum controllable on time and
the output has a low voltage. During the switch on time, the inductor current ramps to the peak current limit
because of the high input voltage and minimum on time. During the switch off time, the inductor would normally
not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The
frequency shift effectively increases the off time allowing the current to ramp down.
(6)
(7)
Where:
I
O
= Output current
I
CL
= Current Limit
V
IN
= Input Voltage
V
OUT
= Output Voltage
V
OUTSC
Output Voltage during short
R
DC
= Inductor resistance
R
HS
= High side MOSFET resistance
R
LS
= Low side MOSFET resistance
t
on
= Controllable on time
fdiv = Frequency divide (equals 1, 2, 4, or 8)
Synchronization to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 19. The square wave amplitude must extend lower than 0.5 V and higher than 1.8V on the RT/CLK pin
and have high and low states greater than 40ns. The synchronization frequency range is 300 kHz to 1100 kHz.
The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external
synchronization circuit should be designed in such a way that the device will have the default frequency set
resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended
to use a frequency set resistor connected as shown in Figure 19 through another resistor (e.g., 50Ω) to ground
for clock signal that are not Hi-Z or tristate during the off state. The sum of the resistance should set the
switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization
signal through a 10pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK threshold
the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage source is removed
and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and lock onto the CLK frequency within 100 microseconds. When the device
transitions from the PLL mode to the resistor mode, the switching frequency will reduce from the external CLK
frequency to 150 kHz, then reapply the 0.5V voltage source and the resistor will then set the switching frequency.
The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions.
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