Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- OVERVIEW
- DETAILED DESCRIPTION
- Fixed Frequency PWM Control
- Slope Compensation Output Current
- Pulse Skip Eco-Mode
- Low Dropout Operation and Bootstrap Voltage (BOOT)
- Error Amplifier
- Voltage Reference
- Adjusting the Output Voltage
- Enable and Adjusting Undervoltage Lockout
- Slow Start/Tracking Pin (SS/TR)
- Overload Recovery Circuit
- Sequencing
- Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- Overcurrent Protection and Frequency Shift
- Selecting the Switching Frequency
- How to Interface to RT/CLK Pin
- Power Good (PWRGD Pin)
- Overvoltage Transient Protection
- Thermal Shutdown
- Small Signal Model for Loop Response
- Simple Small Signal Model for Peak Current Mode Control
- Small Signal Model for Frequency Compensation
- APPLICATION INFORMATION
- Design Guide — Step-By-Step Design Procedure
- Selecting the Switching Frequency
- Output Inductor Selection (LO)
- Output Capacitor
- Catch Diode
- Input Capacitor
- Slow Start Capacitor
- Bootstrap Capacitor Selection
- Under Voltage Lock Out Set Point
- Output Voltage and Feedback Resistors Selection
- Compensation
- Discontinuous Mode and Eco Mode Boundary
- APPLICATION CURVES
- Power Dissipation Estimate
- Layout
- Revision History
DGQ PACKAGE
(TOP VIEW)
PH
GND
COMP
VSENSE
BOOT
VIN
EN
SS/TR
1
2
3
4
10
9
8
7
4
PWRGDRT/CLK
6
5
Thermal
Pad
(11)
DRC PACKAGE
(TOP VIEW)
PH
GND
COMP
VSENSE
BOOT
VIN
EN
SS/TR
1
2
3
4
10
9
8
7
4
PWRGDRT/CLK
6
5
Thermal
Pad
(11)
TPS54060
www.ti.com
SLVS919A –JANUARY 2009–REVISED JULY 2010
DEVICE INFORMATION
PIN CONFIGURATION
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 O
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 8 O
components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
EN 3 I
undervoltage lockout with two resistors.
GND 9 – Ground
PH 10 I The source of the internal high-side power MOSFET.
POWERPAD 11 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
PWRGD 6 O
EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR 4 I
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 60 V.
VSENSE 7 I Inverting node of the transconductance ( gm) error amplifier.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS54060