Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- OVERVIEW
- DETAILED DESCRIPTION
- Fixed Frequency PWM Control
- Slope Compensation Output Current
- Pulse Skip Eco-Mode
- Low Dropout Operation and Bootstrap Voltage (BOOT)
- Error Amplifier
- Voltage Reference
- Adjusting the Output Voltage
- Enable and Adjusting Undervoltage Lockout
- Slow Start/Tracking Pin (SS/TR)
- Overload Recovery Circuit
- Sequencing
- Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- Overcurrent Protection and Frequency Shift
- Selecting the Switching Frequency
- How to Interface to RT/CLK Pin
- Power Good (PWRGD Pin)
- Overvoltage Transient Protection
- Thermal Shutdown
- Small Signal Model for Loop Response
- Simple Small Signal Model for Peak Current Mode Control
- Small Signal Model for Frequency Compensation
- APPLICATION INFORMATION
- Design Guide — Step-By-Step Design Procedure
- Selecting the Switching Frequency
- Output Inductor Selection (LO)
- Output Capacitor
- Catch Diode
- Input Capacitor
- Slow Start Capacitor
- Bootstrap Capacitor Selection
- Under Voltage Lock Out Set Point
- Output Voltage and Feedback Resistors Selection
- Compensation
- Discontinuous Mode and Eco Mode Boundary
- APPLICATION CURVES
- Power Dissipation Estimate
- Layout
- Revision History

V
O
R
ESR
C
OUT
R
L
VC
gm
ps
fp
fz
Adc
Z
OUT
C
P
s
1
2
V
Adc
V
s
1
2
æ ö
+
ç ÷
p ´
è ø
= ´
æ ö
+
ç ÷
p ´
è ø
f
f
ps L
Adc = gm R´
P
OUT L
1
f
C R 2
=
´ ´ p
Z
OUT ESR
1
C R 2
=
´ ´ p
f
TPS54060
SLVS919A –JANUARY 2009–REVISED JULY 2010
www.ti.com
DETAILED DESCRIPTION (continued)
Simple Small Signal Model for Peak Current Mode Control
Figure 47 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54060 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage
transconductance. The gm
PS
for the TPS54060 is 1.9A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
Figure 47. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
(14)
(15)
(16)
(17)
Small Signal Model for Frequency Compensation
The TPS54060 uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 48. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 18 and Equation 19 show how to relate the frequency response of
the amplifier to the small signal model in Figure 48. The open-loop gain and bandwidth are modeled using the R
O
and C
O
shown in Figure 48. See the application section for a design example using a Type 2A network with a
low ESR output capacitor.
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