Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- OVERVIEW
- DETAILED DESCRIPTION
- Fixed Frequency PWM Control
- Slope Compensation Output Current
- Pulse Skip Eco-Mode
- Low Dropout Operation and Bootstrap Voltage (BOOT)
- Error Amplifier
- Voltage Reference
- Adjusting the Output Voltage
- Enable and Adjusting Undervoltage Lockout
- Slow Start/Tracking Pin (SS/TR)
- Overload Recovery Circuit
- Sequencing
- Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- Overcurrent Protection and Frequency Shift
- Selecting the Switching Frequency
- How to Interface to RT/CLK Pin
- Power Good (PWRGD Pin)
- Overvoltage Transient Protection
- Thermal Shutdown
- Small Signal Model for Loop Response
- Simple Small Signal Model for Peak Current Mode Control
- Small Signal Model for Frequency Compensation
- APPLICATION INFORMATION
- Design Guide — Step-By-Step Design Procedure
- Selecting the Switching Frequency
- Output Inductor Selection (LO)
- Output Capacitor
- Catch Diode
- Input Capacitor
- Slow Start Capacitor
- Bootstrap Capacitor Selection
- Under Voltage Lock Out Set Point
- Output Voltage and Feedback Resistors Selection
- Compensation
- Discontinuous Mode and Eco Mode Boundary
- APPLICATION CURVES
- Power Dissipation Estimate
- Layout
- Revision History
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TPS54060
SLVS919A –JANUARY 2009–REVISED JULY 2010
www.ti.com
DETAILED DESCRIPTION (continued)
Figure 43. Plot of Synchronizing in ccm Figure 44. Plot of Synchronizing in dcm
Figure 45. Plot of Synchronizing in PSM
Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor
between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
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